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Parasitic extraction of standalone metal traces (IC6.1.5)

Wes8

Hi,

I have a layout view with multiple metal traces adjacent to one another that I want to simulate as an array of resistors/capacitors. Is there a way to obtain the exact resistance/capacitance of these metal traces through parasitic extraction?

I'm assuming there has to be some sort of linking between the layout of these metal traces and a schematic view in order to run LVS followed by QRC parasitic extraction, but how do you instantiate a standalone metal trace as a resistor/capacitor in schematic view?

Thanks in advanced for any suggestions.

Parents

  •  If the layout view really only has just tracks, you would probably need to use some kind of "metal resistor" to break the track in two and then have a different pin on each end of the track. Often PDKs/rule decks have metal resistors formed by a marker over a metal track which creates a small resistor but has the benefit of splitting the wire into two nets - and consequently you can have a pin on each end then. You'd then be able to have a symbol (and schematic) corresponding to this and so could go through the normal LVS, QRC and parasitic resimulation flow.

    Kind Regards,

    Andrew.

Reply

  •  If the layout view really only has just tracks, you would probably need to use some kind of "metal resistor" to break the track in two and then have a different pin on each end of the track. Often PDKs/rule decks have metal resistors formed by a marker over a metal track which creates a small resistor but has the benefit of splitting the wire into two nets - and consequently you can have a pin on each end then. You'd then be able to have a symbol (and schematic) corresponding to this and so could go through the normal LVS, QRC and parasitic resimulation flow.

    Kind Regards,

    Andrew.

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