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Simulator Inaccuracy?

MTP3

Hi!

I am facing a very interesting issue that I have not seen/experienced before in cadence. I have a delay line and I am interested in finding the delay through it. When I use a vpulse to generate the input signal I get the expected output clock after the expected delay with no unusual effects. But when I generate the input clock using a verilog A block the output is delayed by the correct amount but the duty cycle of the output clock is consideably greater than the input clock.

The rise/fall times, frequency and pulse widths in both cases is exactly the same and the experimental setup is exactly the same. I am running the simulation in conservative preset mode.

Any idea what could be causing the issue and which results to trust. 

Thanks and Regards,

MTP 

  • It seems that odd behaviour was due to my setup referncing the wrong pdk files. The files were updated my machine was still pointing to the old parameters causing the odd behaviour. So a restart now and then does really help :)

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