On how to migrate a design to a new technology, at the schematic level

Hello all!

I would like to ask for your advice on the easiest way of migrating an entire analog design from one technology to a completely different one, at the schematic level (i.e., no layout views involved whatsoever). The situation is as follows.

I have developed a more-or-less large analog design whose library contains dozens of cells (about 80), and which altogether comprise about 7-8 levels of hierarchy (i.e., from the most atomical ones to the top-level). At this point we are only interested on the general behavior of the architecture, and thus the design has been completed only at the schematic level. Luckily enough, the design is made up solely of pmos and nmos transistors (no res, caps, etc), which belong to the vanilla-flavor transistors of a 0.35um CMOS process. Beside these mosfets, the only other components are ideal current sources, used for modeling biasing. Moreover, all the instances of these transistors have their W and L values defined as variables, and in the whole design there are no hard-specified values of any kind. The total number of variables in the final hierarchy is only about 12 (including variables for bias voltages and  currents).

So far, so good. I have successfully validated the performance of the aforementioned design, and now we need to assess how this performance would change when migrating the architecture to a 180um CMOS process. Obviously the most straightforward way to accomplish this would be
to just make a copy of the entire library, attach it to the new technology and then manually edit the most atomic cells for replacing all the pmos and nmos of the old process with their respective
counterparts in the new technology. However, I had tried this and doing it for large cells results rather impractical and very prone to human error. What's more, depending on the performance results of the migrated design it is very likely that we will be interested in further migrating it to other technologies (e.g. 90nm CMOS), thus increasing the manual effort exponentially.  It is therefore clear that this manual approach to cell edition is not a viable solution for migrating the entire architecture.

Taking all this into consideration, I am desperately seeking for an alternative way of translating the design in a more or less automated fashion. I suspect all that is needed to do is editing the atomic cell's netlists for making the appropriate replacement for each transistor instance, a task that could be implemented by code. However, I have never worked seriously at the code level in Cadence, and I have no idea on what to edit, which language to use, nor where to start.

I am quite positive that I can accomplish these goals, but I need help to get started. Please let me know if you have any idea on how to approach the solution to this problem. Any help is appreciated!!!

Thanks so much for any ideas, and sorry for the long post!

Regards,