• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Ultrasim: individual accuracy setting on subcircuit level...

Stats

  • Locked Locked
  • Replies 6
  • Subscribers 131
  • Views 17685
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Ultrasim: individual accuracy setting on subcircuit level ?

baenischfau
baenischfau over 11 years ago

Hi all,

 

I'm currently simulating a big mixed signal block, consisting of two big blocks. The instance block I0 is

pure digital logic, instance I1 is mainly analog but also includes some digital parts. I'm using Ultrasim

for verification but due to the analog parts I'm forced to use a quite strict accuracy setting to get the

results about right. However this setting is killing the digital part ...

 

I know that some other simulators offer the possibility to define accuracy levels for each instance in

a design, e.g. set I0 to Digital Fast and I1 to Analog. Is something like this possible with Ultrasim ?

 

Best Regards

 

Andi

  • Cancel
Parents
  • Jagdish23
    Jagdish23 over 10 years ago

    Hi Andrew, I am currently using AMS simulator with ultrasim solver. I have a question. If I mention sim_mode and speed for a sub-block which is digital block(verilog view) then will this digital block solved by analog(ultrasim) solver, or the simulator will just ignore the sim_mode and speed option specified for this block and block will be simulated by digital solver? And for a analog block I do not mention any of sim_mode or speed, then what is the default mode the simulator will consider?

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Jagdish23
    Jagdish23 over 10 years ago

    Hi Andrew, I am currently using AMS simulator with ultrasim solver. I have a question. If I mention sim_mode and speed for a sub-block which is digital block(verilog view) then will this digital block solved by analog(ultrasim) solver, or the simulator will just ignore the sim_mode and speed option specified for this block and block will be simulated by digital solver? And for a analog block I do not mention any of sim_mode or speed, then what is the default mode the simulator will consider?

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information