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Ultrasim: individual accuracy setting on subcircuit level ?

baenischfau

Hi all,

 

I'm currently simulating a big mixed signal block, consisting of two big blocks. The instance block I0 is

pure digital logic, instance I1 is mainly analog but also includes some digital parts. I'm using Ultrasim

for verification but due to the analog parts I'm forced to use a quite strict accuracy setting to get the

results about right. However this setting is killing the digital part ...

 

I know that some other simulators offer the possibility to define accuracy levels for each instance in

a design, e.g. set I0 to Digital Fast and I1 to Analog. Is something like this possible with Ultrasim ?

 

Best Regards

 

Andi

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  • PNadeau

    Not sure if this was resolved, but for anyone else coming across this, there is actually a magic button that you have to set to make this work.

    After you set the config view the way you like it, go back to ADE (or ADEXL) and go to Simulation->Options->FastSpice->Miscellaneous.  Click "Allow usim_opt in HED."  Now it should work.

    Also, the option directly above allows you to specify usim_opt's on the schematic instead.  For example, you can "q" schematic instances and add a user variable "usim_opt" and specifying strings like "sim_mode=s speed=1"...

    For what it's worth, in simulating large mixed signal designs with Ultrasim, another critical option for me was judicious use of the "Voltage regulator" option if you have any VR's, or in my case, for power gating switches.  From what I understand, this is because Ultrasim is not able to take advantage of the simplified MOS models if it doesn't see sources of devices connected to stable supplies (like vdc's or gnds), so the 1000's of digital transistors connected to a power switch (or VR) will be simulated at much higher accuracy than they need to be.  When I finally realized I should apply this option, I received a very large speed-up.

    Cheers,

    Phil

Reply
  • PNadeau

    Not sure if this was resolved, but for anyone else coming across this, there is actually a magic button that you have to set to make this work.

    After you set the config view the way you like it, go back to ADE (or ADEXL) and go to Simulation->Options->FastSpice->Miscellaneous.  Click "Allow usim_opt in HED."  Now it should work.

    Also, the option directly above allows you to specify usim_opt's on the schematic instead.  For example, you can "q" schematic instances and add a user variable "usim_opt" and specifying strings like "sim_mode=s speed=1"...

    For what it's worth, in simulating large mixed signal designs with Ultrasim, another critical option for me was judicious use of the "Voltage regulator" option if you have any VR's, or in my case, for power gating switches.  From what I understand, this is because Ultrasim is not able to take advantage of the simplified MOS models if it doesn't see sources of devices connected to stable supplies (like vdc's or gnds), so the 1000's of digital transistors connected to a power switch (or VR) will be simulated at much higher accuracy than they need to be.  When I finally realized I should apply this option, I received a very large speed-up.

    Cheers,

    Phil

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