Stats

  • Locked Locked
  • Replies 1
  • Subscribers 124
  • Views 14608
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

veriloga capacitor model

archive

hi,

i have defined a capacitor using the following statement v(p,n)

thanks,
Anisha


Originally posted in cdnusers.org by anisha_r

  • Probably you should report this to customer support - I suspect we need to add some support for an attribute so that the expression can be identified as being a capacitor.

    As a workaround, you could instantiate a primitive capacitor using a structural instantiation within the Verilog-A. i..e

    capacitor #(.c(C)) C1(p,n);

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.