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veriloga capacitor model

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hi,

i have defined a capacitor using the following statement v(p,n)

thanks,
Anisha


Originally posted in cdnusers.org by anisha_r
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    Probably you should report this to customer support - I suspect we need to add some support for an attribute so that the expression can be identified as being a capacitor.

    As a workaround, you could instantiate a primitive capacitor using a structural instantiation within the Verilog-A. i..e

    capacitor #(.c(C)) C1(p,n);

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett

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