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LVS issue: short between global net VSS! and gnd

isazulkc

Hi,

I' m using PVS 12.1 in IC6 to do LVS and  I have that issue:

One cell used in the schematic has a global net VSS! and VDD!. In the top schematic and layout,the power is vdd and ground is vss.

So the LVS fails and complains about VSS! shorted to vss and VDD! shorted with vdd. Is there a way to make the LVS understand there are the same net and to not have an LVS fail ?

 Regards,

KC

  • Andrew Beckett

    KC,

    Probably you just need to add a basic/cds_thru component in your top level schematic which connects between VSS! and vss and so on.

    Depending on the version you're using, this will end up in the CDL netlist either as a *.CONNECT statement or a small-value resistor - if the latter, you can set the lower threshold for resistors on the Export CDL form, and any resistor smaller than that will get shorted.

    So consequently, you will have captured the short on the schematic which matches the layout, and all should be OK (hopefully).

    Regards,

    Andrew.

  • isazulkc

    Hi Andrew,

    The cds_thru generated a 100 mOhms resistance that don't directly pass LVS. Finally, I just had to edit/add  netset properties to the cell to link the global net in its schematic to the real power and ground in the top schematic.

    Thanks,

    Regards,

    KC 

  • Nhumai
    in reply to isazulkc

    Hi KC 

    I have a same problem can you please share how you do that ? 

    thanks 

    Nhumai 

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