• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Driving an internal node several heirarchical layers down...

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 15001
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Driving an internal node several heirarchical layers down...

deklein
deklein over 11 years ago

All,

First, an apology. I am new to ADE XL and spectre, coming from hspice and MICA, so if I am asking a really obvious question, please pardon my ignorance. However, in my defence, this is stumping the local ADE XL expert. I have tried various searches of the forums and google without luck. So here goes:

Suppose I have a schematic with an instance of a cell (A) in it. In this instance, there is another instance of cell (B). Now, futher suppose that to test the recovery of a circuit from a particular un-toward upset, I need to reach through the heirarchy and manipulate the voltage on a net in B that I'll call z. I do not have z as a pin on either B or A, it is simply a labeled wire in B. How do I do this?

I've tried doing netsets, net expressions, declaring as global nets, etc. but either I am going it wrong, or it isn't working. And, while bringing this net out to a pin and then up through the heirarchy is possible, it would be a very ugly solution and probably cause trouble when this particular block is wrapped up for P&R. That is, the example I give here is very simple. The actual test case not so much.

I ask because were I running hspice from the command line, I would have a command in the control deck that looked something like this and be done:

gbreakB    xA.xB.z vss vcr pwl(1) verr gnd 0,1e12 1,1e5 2,1 3,1e-5

That is, as I sweep verr from 0v -> 3v, I effectively short z to vss, causing the upset condition in B.

Thanks,

Dave

  • Cancel
  • Andrew Beckett
    Andrew Beckett over 11 years ago

    Hi Dave,

    You can do this in spectre too. Simply do:

    vbreak (I1.I2.z vss) vsource type=pulse ...

    in spectre syntax. If you are doing this from a schematic (which is presumably the case) you can use the deepprobe component that I created a few years ago as described in this solution. Since there's no support in the schematic editor for doing an out-of-cellView reference, this component allows you to place a component on your schematic where the parameter is the hierarchical node name; it instantiates an iprobe (a zero-volt source) between that hierarchical node and the pin of the instance - so you can then connect whatever you like down through the hierarchy. Obviously this is for testbench use only - more details in the solution.

    Regards,

    Andrew.

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information