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veriloga module library association

mystika

Hi guys,

I created a module in veriloga instantiating other modules like the resistors and capacitors found in the ahdlLib

cap #(.c(1)) Cx(x, gnd);

res #(.r(1T)) Raux(x, gnd);

res #(.r(Rofff)) Roff(aux, minus); 

the structure says it is associated with the analogLib with the view symbol.

Structure summary for module "test1"

    child          bound to (library view)

    --------------------------------------

    Cx             (analogLib - view symbol)

    Raux           (analogLib - view symbol)

    Roff           (analogLib - view symbol) 

My question is how do I bind the components to the ahdlLib or custom modules for the resistor and capacitor because when I run simulation I get these errors:

ERROR (SFE-23): "" 33: Cx is an instance of an undefined model cap.

ERROR (SFE-23): "" 34: Raux is an instance of an undefined model res.

 ERROR (SFE-23): "" 35: Roff is an instance of an undefined model res. 

 Thanks 

Parents
  • Andrew Beckett

    Use "capacitor" and "resistor" instead so that you are binding to the primitive devices in the simulator.

    Regards,

    Andrew.

  • billnxp
    in reply to Andrew Beckett

    Hi Andrew, I know this is an old post,  but I've a related problem that may be of interest to anyone finding this post.
    I did use 'capacitor'  for my veriloga instance expecting to get the primitive.  EG ...

    // input caps
    capacitor #(.c(cin)) Cinput(dom_vdd, vsshp);
    capacitor #(.c(cin)) Cenab(enablels_vcc, vsshp);
    capacitor #(.c(cin)) Cdisab(disablels_vcc, vsshp);
    endmodule

    But in the HED config view I see that it wants to bind these instances to something else.  How do I fix this problem?

    (Here I selected a 'vew = bbt' to force the binding into the config file).

    cell smgBasicMSLib.capacitor binding :bbt;

    Why does it not get the correct primitive association ?

Reply
  • billnxp
    in reply to Andrew Beckett

    Hi Andrew, I know this is an old post,  but I've a related problem that may be of interest to anyone finding this post.
    I did use 'capacitor'  for my veriloga instance expecting to get the primitive.  EG ...

    // input caps
    capacitor #(.c(cin)) Cinput(dom_vdd, vsshp);
    capacitor #(.c(cin)) Cenab(enablels_vcc, vsshp);
    capacitor #(.c(cin)) Cdisab(disablels_vcc, vsshp);
    endmodule

    But in the HED config view I see that it wants to bind these instances to something else.  How do I fix this problem?

    (Here I selected a 'vew = bbt' to force the binding into the config file).

    cell smgBasicMSLib.capacitor binding :bbt;

    Why does it not get the correct primitive association ?

Children
  • Andrew Beckett
    in reply to billnxp

    This is something that's slightly awkward in how ADE handles it. Probably the simplest solution is to add the sample library into your cds.lib using:

    define sample $(inst_root_with:tools/dfII/bin/virtuoso)/tools/dfII/samples/cdslib/sample

    You'll then need to do the "check and save" of the VerilogA view again, but then the hierarchy editor won't complain and ADE should be able to netlist OK.

    Alternatively, in HED find your cell with the veriloga view containing these capacitors, and do right mouse->Add Stop Point. This will stop the netlister trying to expand the hierarchy within the VerilogA view and then it won't complain about the missing view binding, and the netlister should succeed too.

    Regards,

    Andrew.

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