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initial condition in spectre verilog simulator

hi

I have a memory design which is 32X32 cell in size and i need to initialize each cell to a value. i.e. around 2048 (1024 bit +1024 bitbar) nodes.

So is there any way other than using Simulation>converegnce aid > initial condition in the analog environment, like using a script or something else which makes the job easier.

thanks,
Siddharth

Originally posted in cdnusers.org by siddharth

archive over 17 years ago

You can create an include file using the "ic" statement (see "spectre -h ic") and then reference this through the Setup->Model Libraries form in ADE.

Regards,

Andrew.

Originally posted in cdnusers.org by adbeckett
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archive over 17 years ago

thank you ....

Originally posted in cdnusers.org by siddharth
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