Netlist error when using Global Sources in hierarchy editor

This happens when I try to use global source in post layout simulations.

The circuit under test is designed with a global source. And I believe the pin names are vdd!/gnd! because I have passed the LVS successfully. But when I try to use hierarchy editor to do the post-layout simulation, it goes wrong. If I compile the schematic view of the circuit with its test circuit, it works well and I get the right simulation result. But if I compile the extracted view of it, it turns out to be wrong. So I check the netlist of it and find that it automatically changed the global source vdd!/gnd! to _net0/_net1. I think it may recognize the two vdd!/gnd! in extracted view of circuit under test and schematic view of test circuit to be a violation of same name and changed it automatically. But they are definitely the same. They are the global sources.

Do you guys know whether there are any settings to fix this? I have looked into many tutorial and they do the post-layout simulation right the same way with no problem. So I think there may be some basic setting errors in my environment. By the way, I’m using IC 5.1.41