Stats

  • Locked Locked
  • Replies 3
  • Subscribers 124
  • Views 14050
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Weird PAC simulation results

archive

Recently I encountered some problems with PAC simulations so I decided to test the PAC simulation. I built the simple RC circuit with the R replaced by a switched-capacitor CR as shown in the following figure: Vin -------(phi 1) -------(phi 2) ----------Vout | | ------ ------ CR | | ------ gnd phi1 and phi2 are non-overlapping clocks controlling two NMOS switches respectively. Vout is connected to the ground (gnd) through another capacitor (not shown). To verify the simulation issues, I constructed three similar circuits as follows (all with same input Vin and clock signals): Circuit (1): NMOS model set 1, Vout = vosci Circuit (2): NMOS model set 2, Vout = vosc Circuit (3): Switched capacitor CR is replaced by its equivalent resistor R, Vout = vorc. PSS simulations are similar for vosci and vosc while vorc is simply a dc voltage as expected. However, when proceeding to perform the PAC simulation, I obtained the following results (see attached). From the graphs, it can be seen that vosci (Circuit 1) and vorc are as expected from simple RC circuit but vosc (Circuit 2) is very odd with a gain of below -100dB. As the only difference between Circuit (1) and Circuit (2) is the NMOS model (BSIM3), could anyone help me solve the weird PAC results mystery? Thanks!


Originally posted in cdnusers.org by harmonics
pacsim.pdf
Parents

  • Thanks, but that doesn't really tell me anything I didn't already know. I doubt it's the models - more likely to be the testbench or simulation setup.

    Also, you've only shown me the circuit, and not the testbench, or the analysis setup, or the models. There are an awful lot more variables where something could be wrong with the setup.

    That's why I suggested going to customer support (sourcelink.cadence.com) - we (Cadence) can then work with you to understand fully the problem, reproduce it, and hopefully correct what's not right with the setup (or fix the tool if something really is wrong with it).

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
Reply

  • Thanks, but that doesn't really tell me anything I didn't already know. I doubt it's the models - more likely to be the testbench or simulation setup.

    Also, you've only shown me the circuit, and not the testbench, or the analysis setup, or the models. There are an awful lot more variables where something could be wrong with the setup.

    That's why I suggested going to customer support (sourcelink.cadence.com) - we (Cadence) can then work with you to understand fully the problem, reproduce it, and hopefully correct what's not right with the setup (or fix the tool if something really is wrong with it).

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.