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VerilogA definitions from ADE-XL

daasboe

Hi,

I would like to be able to make a VerilogA `define in Cadence ADE-XL environment. Is that possible to do? The reason for this is that I want to have the same VerilogA module and symbol, and change sequence depending on what simulation I am running (`include different files). Is there another way to do it?

BR,
Daniel 

  • Daniel,

    From "spectre -h":

         -va,define MACRO[=value]
                      Defines a macro with higher priority than the one defined in Verilog-A files.

    So you should be able to add "-va,define MACRO=value" in the usrCmdLineOption field in Setup->Environment in the test editor.

    Maybe that does what you want?

    Regards,

    Andrew

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