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  3. Disable instances in Schematic

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Disable instances in Schematic

Zdeno
Zdeno over 11 years ago

Hi Cadence users,

is there any option how to disable/deactivated instance in schematic editor for simulation purpose - add/remove parasitic components?

Thank you very much.

Zdenko

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  • Andrew Beckett
    Andrew Beckett over 11 years ago

    You can cause a component to be omitted by adding a property on it, nlAction="ignore", or nlIgnore="spectre". Or if you have a config, you can use bind to open on the instance which will cause it to be omitted. Note that this just omits the instance - which is fine for a capacitor. For a resistor, this approach wouldn't work - which you could do is have a resistor with a schematic underneath which contains an iprobe to connect the two pins - and you could use the hierarchy editor to either pick the spectre view (which could netlist as a resistor) or the schematic view (which would netlist as a short).

    Alternatively, ADE GXL has a means of creating parasitic estimates via the "PAD" flow (see the documentation for more detail) which allows you to add parasitics to your schematic without actually editing the schematic. You can then simulate with the "estimated" view which is built from the schematic plus the information on parasitics you want to add. This is the cleanest approach.

    Kind Regards,

    Andrew.

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  • Meysam Z
    Meysam Z over 6 years ago in reply to Andrew Beckett

    Dear Andrew, Is it possible to use nlIgnore to have the simulator ignore an instance when config is pointing to veriloga but netlisting it when schematic is selected, Basically I have back to back inverters between clock lines and verilog-A sees that as a loop and does not like it. So I need to ignore them for verilog-a however for performance sims, I dont want those inverters to be present. 

    Any suggestions?

    Regards

    Meysam

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  • Meysam Z
    Meysam Z over 6 years ago in reply to Andrew Beckett

    Dear Andrew, Is it possible to use nlIgnore to have the simulator ignore an instance when config is pointing to veriloga but netlisting it when schematic is selected, Basically I have back to back inverters between clock lines and verilog-A sees that as a loop and does not like it. So I need to ignore them for verilog-a however for performance sims, I dont want those inverters to be present. 

    Any suggestions?

    Regards

    Meysam

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  • Andrew Beckett
    Andrew Beckett over 6 years ago in reply to Meysam Z

    Meysam,

    I don't really understand what you're asking here. You can't do this with nlIgnore, although you could choose to use "bind to open" in the config to omit various instances or cells when changing the views to use in the hierarchy editor. However, it sounds to me as if you just need to fix the "loop" (presumably a loop of rigid branches, although you've not provided much info) rather than trying to come up with a dirty flow to make this work.

    BTW, posting on the end of a 5 year old thread is not a good idea - the forum guidelines ask you not to do this as it confuses the thread for anyone who is searching for similar issues.

    Regards,

    Andrew.

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