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Intrinsic capacitance Cbs

ronaldomponte

I am simulating a conventional ring oscilator with pmos and nmos devices comprising the inverter cell.

Bulk and source terminals are shorted, so Vsb = 0. 

As the intrinsic capacitive coefficients are defined as Cij = dQj/dVj in Bsim3v3 model, it should be predicted that the Cbs = 0 (since Vs=0).

However, inspecting the nfet and pfet DC operating points, it can be seen that the Cbs capacitance is not null.  Even more, its magnitude is as large as the Cgg magnitude, for instance. Is that correct? What am I missing?

Thank you very much for clarifing that.

 

 

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  •  Dear ronalsomponte,

     I understand your question. I'll throw in my thoughts concerning the matter for your thoughts or the thoughts of anyone else reading this...

     I do not believe the fact that they are finite instead of 0 will significantly impact the schematic view based simulation results of your ring VCO. Since in the schematic view of your netlist, the bulk and source terminals are shorted, the voltage across them is zero and not changing with time. As a result, the displacement current across this capacitance will be zero since i =Cbs(dv/dt).

    However, should you decide to create a physical layout of your circuit and create an extracted view based netlist, it is possible some trace or via resistance will be present between the BSIM3 source and bulk terminals. As a result, in a transient simulation, a voltage difference may exist that varies with time between the source and bulk terminals. If the value of Cbs were set to 0 fF, the current through this path would necessarily be zero. However, since physically a voltage difference can occur between the two terminals with time due to the layout parasitics, there will be some displacement current. With a defined value of Cbs of 0F, this displacement current will not be captured in the transient simulation results

    I hope this explains my thoughts on the issue ronaldomponte...let me know if it is not clear!

    Shawn

Reply

  •  Dear ronalsomponte,

     I understand your question. I'll throw in my thoughts concerning the matter for your thoughts or the thoughts of anyone else reading this...

     I do not believe the fact that they are finite instead of 0 will significantly impact the schematic view based simulation results of your ring VCO. Since in the schematic view of your netlist, the bulk and source terminals are shorted, the voltage across them is zero and not changing with time. As a result, the displacement current across this capacitance will be zero since i =Cbs(dv/dt).

    However, should you decide to create a physical layout of your circuit and create an extracted view based netlist, it is possible some trace or via resistance will be present between the BSIM3 source and bulk terminals. As a result, in a transient simulation, a voltage difference may exist that varies with time between the source and bulk terminals. If the value of Cbs were set to 0 fF, the current through this path would necessarily be zero. However, since physically a voltage difference can occur between the two terminals with time due to the layout parasitics, there will be some displacement current. With a defined value of Cbs of 0F, this displacement current will not be captured in the transient simulation results

    I hope this explains my thoughts on the issue ronaldomponte...let me know if it is not clear!

    Shawn

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