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Intrinsic capacitance Cbs

ronaldomponte

I am simulating a conventional ring oscilator with pmos and nmos devices comprising the inverter cell.

Bulk and source terminals are shorted, so Vsb = 0. 

As the intrinsic capacitive coefficients are defined as Cij = dQj/dVj in Bsim3v3 model, it should be predicted that the Cbs = 0 (since Vs=0).

However, inspecting the nfet and pfet DC operating points, it can be seen that the Cbs capacitance is not null.  Even more, its magnitude is as large as the Cgg magnitude, for instance. Is that correct? What am I missing?

Thank you very much for clarifing that.

 

 

Parents
  • Dear Shawn,
     
    Thank you very much for your quick reply.
    I believe I understand your answer, but let me make sure of this.
    Summarizing your aforementioned thoughts, the nonzero Cbs lies on the fact that the parasitics between source and bulk contacts (arising from layout) may contribute to some displacement current. Thus, a nonzero Vsb may arise so that the Cbs is not 0 fF.
    This make sense for me, but how the simulator can present this nonzero Cbs in the simulation results of the schematic view but the layout has not been initiated, yet. The simulator estimates the layout parasitics and accounts for in the schematic view?
    Thank you very much again. 
     
Reply
  • Dear Shawn,
     
    Thank you very much for your quick reply.
    I believe I understand your answer, but let me make sure of this.
    Summarizing your aforementioned thoughts, the nonzero Cbs lies on the fact that the parasitics between source and bulk contacts (arising from layout) may contribute to some displacement current. Thus, a nonzero Vsb may arise so that the Cbs is not 0 fF.
    This make sense for me, but how the simulator can present this nonzero Cbs in the simulation results of the schematic view but the layout has not been initiated, yet. The simulator estimates the layout parasitics and accounts for in the schematic view?
    Thank you very much again. 
     
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