• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. CDR for USB 3.0 PHY

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 125
  • Views 14020
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

CDR for USB 3.0 PHY

Jithin
Jithin over 11 years ago
Sir,
     I am modeling a Dual loop CDR for USB 3.0 PHY. As per jitter budgeting of USB 3.0, it specifies a deterministic jitter of 143pSec and random jitter of 4.03pSec. As I was trying to model random jitter using Verilog A function $dist_normal (seed, mean, sd) with mean=0 and sd=4.03p and similarly deterministic jitter using $dist_uniform (seed, start, end) with start= -71.5p and end= 71.5p, my CDR was unable to track data having deterministic jitter of 143pSec for a data rate of 5Gbps (but CDR tracks data if the jitter value is half of the specified above, that is below 80ps). So my query is that,
 
     Is this the right way to model deterministic jitter and random jitter? And also do we have to add this much of Jitter into the data for a data rate of 5Gbps?
Thanks and Regards,
Jithin 
  • Cancel
  • ShawnLogan
    ShawnLogan over 11 years ago

     Dear Jithin,

     > Is this the right way to model deterministic jitter and random jitter?

    I do not think your model accurately captures the frequency characterstics of the entire channel. Specifically, from the USB 3.0 standard, the TX components of the random and deterministic jitter are specified after the application of the appropriate jitter transfer function (Note 6, Table 6-8 of standard). As such, the magnitude of the random and deterministic jitter components will vary with frequency. Similarly, the receiver jitter components will also vary with frequency and I am not sure how you are capturing that in your model.

    As a result of using your model, when you simulate the CDR, that has a known jitter tolerance depending on its bandwidth, you may be applying far too much jitter at frequencies beyond the tracking capability of the CDR. This will reduce the eye margin and may lead to bit errors.

     > And also do we have to add this much of Jitter into the data for a data rate of 5Gbps?

     I would recommend, Jithin, that you study the USB 3.0 document entitled "USB Superspeed Compliance Methodology" and the USB 3.0 receiever and transmitter physical layer compliance sections of the USB 3.0 standard to create a more accurate model of the pertinent noise profiles.

     

    I hope this helps,

    Shawn

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • Jithin
    Jithin over 11 years ago
    Sir, First of all I would like to thank you for your quick reply and also its been a very fruitful advice. Regards, Jithin
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information