How to define a binary matrix parameter in Verilog A

Hi guys, I have a question about how to define a binary matrix parameter in Verilog A. For example, I can define parameter as data_pattern[15:0]={0,0,0,.....,0}. To my knowledge, each bit of data_pattern[15:0] are 32bit integer, for me I only want data_pattern to be a 16-bit binary.

After run the code (attach on this post), the data_pattern[0] returned to be 0111111111111111111111111111111 instead of a 32bit "0", which makes the final verilog module incorrect.

 Also no matter how the data_pattern set throught cadence instantce interface, the output is still unchanged. Means the data_pattern parameter can not be changed without changing the code.

 Thank you for your help in advance!!