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How to define a binary matrix parameter in Verilog A

Hi guys, I have a question about how to define a binary matrix parameter in Verilog A. For example, I can define parameter as data_pattern[15:0]={0,0,0,.....,0}. To my knowledge, each bit of data_pattern[15:0] are 32bit integer, for me I only want data_pattern to be a 16-bit binary.

After run the code (attach on this post), the data_pattern[0] returned to be 0111111111111111111111111111111 instead of a 32bit "0", which makes the final verilog module incorrect.

Also no matter how the data_pattern set throught cadence instantce interface, the output is still unchanged. Means the data_pattern parameter can not be changed without changing the code.

Thank you for your help in advance!!

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microstudent over 11 years ago

Thank you Andrew, here is the heading of my spectre.out .
Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 10.1.1.441.isr25 32bit 25 Jul 2012 Copyright (C) 1989-2012 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc.
Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782; 7,085,700; 7,143,021; 7,493,240; 7,571,401.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: yangli Host: ccl HostID: 7F0100
PID: 3300 Memory available: 99.8917 GB physical: 151.9494 GB CPU Type: Intel(R) Xeon(R) CPU E5-2690 0 O. 2.90GHz Processor PhysicallD CoreID Frequency
0 0 0 2900.1 1 1 0 2900.1 2 0 1 2900.1 3 1 1 2900.1 4 0 2 2900.1 5 1 2 2900.1 6 0 3 2900.1 7 1 3 2900.1 8 0 4 2900.1 9 1 4 2900.1 10 0 5 2900.1 11 1 5 2900.1 12 0 6 2900.1 13 1 6 2900.1 14 0 7 2900.1 15 1 7 2900.1

Simulating 'input.scs' on ccl at 5:18:22 PM, Wed Jun 4, 2014 (process id: 3300).
Command line: /cadtools/cadence/MMSIM101/tools.lnx86/spectre/bin/32bit/spectre \ -env artist5.1.0 +escchars +log ../psf/spectre.out +inter=mpsc \ +mpssession=spectre5_7560_62 -format sst2 -raw \ -I/cadtools/pdk/towerjazz/cis018/HOTCODE/models/v4.51/spectre \ +lqtimeout 900 -many 5 -main 5 input.scs spectre pid = 3300 Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libphilips_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libsparam_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so Time for NDB Parsing: CPU = 263.959 ms, elapsed = 287.039 ms. Time accumulated: CPU = 263.959 ms, elapsed = 287.039 ms. Peak resident memory used = 27.1 Mbytes.
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microstudent over 11 years ago

Thank you Andrew, here is the heading of my spectre.out .
Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 10.1.1.441.isr25 32bit 25 Jul 2012 Copyright (C) 1989-2012 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc.
Protected by U.S. Patents: 5,610,847; 5,790,436; 5,812,431; 5,859,785; 5,949,992; 5,987,238; 6,088,523; 6,101,323; 6,151,698; 6,181,754; 6,260,176; 6,278,964; 6,349,272; 6,374,390; 6,493,849; 6,504,885; 6,618,837; 6,636,839; 6,778,025; 6,832,358; 6,851,097; 6,928,626; 7,024,652; 7,035,782; 7,085,700; 7,143,021; 7,493,240; 7,571,401.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc. User: yangli Host: ccl HostID: 7F0100
PID: 3300 Memory available: 99.8917 GB physical: 151.9494 GB CPU Type: Intel(R) Xeon(R) CPU E5-2690 0 O. 2.90GHz Processor PhysicallD CoreID Frequency
0 0 0 2900.1 1 1 0 2900.1 2 0 1 2900.1 3 1 1 2900.1 4 0 2 2900.1 5 1 2 2900.1 6 0 3 2900.1 7 1 3 2900.1 8 0 4 2900.1 9 1 4 2900.1 10 0 5 2900.1 11 1 5 2900.1 12 0 6 2900.1 13 1 6 2900.1 14 0 7 2900.1 15 1 7 2900.1

Simulating 'input.scs' on ccl at 5:18:22 PM, Wed Jun 4, 2014 (process id: 3300).
Command line: /cadtools/cadence/MMSIM101/tools.lnx86/spectre/bin/32bit/spectre \ -env artist5.1.0 +escchars +log ../psf/spectre.out +inter=mpsc \ +mpssession=spectre5_7560_62 -format sst2 -raw \ -I/cadtools/pdk/towerjazz/cis018/HOTCODE/models/v4.51/spectre \ +lqtimeout 900 -many 5 -main 5 input.scs spectre pid = 3300 Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libphilips_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libsparam_sh.so Loading /cadtools/cadence/MMSIM101/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so Time for NDB Parsing: CPU = 263.959 ms, elapsed = 287.039 ms. Time accumulated: CPU = 263.959 ms, elapsed = 287.039 ms. Peak resident memory used = 27.1 Mbytes.
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