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  3. Addition of source with know statistical data

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Addition of source with know statistical data

archive
archive over 17 years ago

    Hi All,

I would like to run a monte carlo simulation on my analog design. I know the statistical distribution (gaussian shaped) of the input signal I have to provide to my system.

Does anyone know how to provide this information to a source like VDC in analogLib library?

Thanks for your support,
Best regards,

Axel


Originally posted in cdnusers.org by axp
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  • archive
    archive over 17 years ago

    Create a file with a ".scs" suffix, and set up the distribution you want (see "spectre -h montecarlo" for more details.

    Then reference this file with Setup->Model Libraries in ADE. In the ADE variables, define variable MYDC, and give it a value (this will be your mean value).

    // statistics block for my
    // design variables
    
    statistics {
    
       process {
          vary MYDC dist=unif N=0.3
          }
    
       mismatch {
          vary MYDC dist=gauss std=0.05
       }
    
    }
    

    On an instance of the vsource, you can use the design variable "MYDC". If you want mismatch to be modelled, you'll need to ensure that the vsource is within a subckt - so create an additional level of hierarchy around the vsource in order to do this.

    That's it.

    Regards, Andrew.


    Originally posted in cdnusers.org by adbeckett
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  • archive
    archive over 17 years ago

    Create a file with a ".scs" suffix, and set up the distribution you want (see "spectre -h montecarlo" for more details.

    Then reference this file with Setup->Model Libraries in ADE. In the ADE variables, define variable MYDC, and give it a value (this will be your mean value).

    // statistics block for my
    // design variables
    
    statistics {
    
       process {
          vary MYDC dist=unif N=0.3
          }
    
       mismatch {
          vary MYDC dist=gauss std=0.05
       }
    
    }
    

    On an instance of the vsource, you can use the design variable "MYDC". If you want mismatch to be modelled, you'll need to ensure that the vsource is within a subckt - so create an additional level of hierarchy around the vsource in order to do this.

    That's it.

    Regards, Andrew.


    Originally posted in cdnusers.org by adbeckett
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