Custom deep trench capacitor

Hi,

I am starting out with a project on DRAM memory cells and am using the cadence 45nm tech node. But at this technology, the capacitance from the mimcap and moscaps need a large area. So I was wondering whether there is any way I would be able to add a custom deep trench capacitor to the technology. Please guide me on what I can do at this point to get about 30-50f of capacitance in a small area preferable deep trench since that wouldn't consume so much space on the die. I am thinking of using sentaurus to simulate the capacitance and import the model as spice model into virtuoso. Please tell me whether this can be done. Or is there a simpler way? And could you point me to some application note that uses this or some references about the above?

thanks