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Custom deep trench capacitor

madhanmo

Hi,

I am starting out with a project on DRAM memory cells and am using the cadence 45nm tech node. But at this technology, the capacitance from the mimcap and moscaps need a large area. So I was wondering whether there is any way I would be able to add a custom deep trench capacitor to the technology. Please guide me on what I can do at this point to get about 30-50f of capacitance in a small area preferable deep trench since that wouldn't consume so much space on the die. I am thinking of using sentaurus to simulate the capacitance and import the model as spice model into virtuoso. Please tell me whether this can be done. Or is there a simpler way? And could you point me to some application note that uses this or some references about the above?

 

thanks

Parents

  • Not really. If you're trying to create something vaguely realistic, then you probably would need to introduce some different layer to indicate that this is different. You'd then need to modify the pcell to alter how the layout is drawn, alter the simulation models to reflect the higher capacitance per unit area, the CDF callbacks to compute dimensions from capacitance, and so on. Not so easy if you don't have the source code of the PDK, so you may be better off creating your own device.

    That's far more than I can realistically do in a few minutes of help in my spare time (especially as the requirements are rather vague). You might be able to go to customer support to ask for help, but I'm guessing you're from a University (since if you were in industry you'd presumably be building something on a real process), but even then this is really beyond what customer support normally provides. There are some documents on Cadence Online Support which cover creation of PDKs, and maybe that's the kind of help customer support can point you at?

    Regards

    Andrew.

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  • Not really. If you're trying to create something vaguely realistic, then you probably would need to introduce some different layer to indicate that this is different. You'd then need to modify the pcell to alter how the layout is drawn, alter the simulation models to reflect the higher capacitance per unit area, the CDF callbacks to compute dimensions from capacitance, and so on. Not so easy if you don't have the source code of the PDK, so you may be better off creating your own device.

    That's far more than I can realistically do in a few minutes of help in my spare time (especially as the requirements are rather vague). You might be able to go to customer support to ask for help, but I'm guessing you're from a University (since if you were in industry you'd presumably be building something on a real process), but even then this is really beyond what customer support normally provides. There are some documents on Cadence Online Support which cover creation of PDKs, and maybe that's the kind of help customer support can point you at?

    Regards

    Andrew.

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