I am using Cadence Virtuoso 6.1.2.
Can you please guide me how to create .v files from a schematic ( lets say of an inverter)?
Also, I wish to create .lef file of my standard cell layout design through
Abgen.But I get error ABS 218 amd ABS - 262. I have fixed those errors,
still it is a problem. Do you know any other way to get -
1. .v files ( gate-level netlist - design files)
2 .lef files ( layout info )
3. .lib files ( timing info )
Hi Aseem1. You can generate a verilog netlist from the schematic using "Launch->Simulation->NC-Verilog" function. This requires a license.2. You will need to use abstract generator to generate the lef file. Would you please provide more details on the errors?3. Please use a cell characterization tool such as Liberate.Best regardsQuek