Problem Photodiode modelling in Verilog-A

Hello everyone, 

 So basically I'm working on my final year project where I have to Design a Camera. The front end of the circuitry is a photodiode. Because the foundries don't provide models, I had to design my own in Verilog-A.

The model is based on the drift and diffusion currents, diode & dark current; and the depletion capacitance. The model may be crude but it will serve my purpose. I've attached my code to the post.

 I'm having two big issues and I can't get a hold off them. I'm just beginning in Verilog-A and I'd like to know if the problem comes from the code itself or my design.

 Basically after I reset the photodiode, the photogenerated current should drain the current from the capacitance and therefore discharge it (I'm operating in reverse bias mode). So the photogenerated current should be negative, which I do in the code (-Iaa). The problem is when I do that the photodiode does not discharge and stays at the reset voltage. I need to put a positive photogenerated current (+Iaa) to get the correct voltage output.

The second problem is even though it discharges, it never goes to 0 but to negative voltages. Which increases when I decrease the light power. 

I've attached the 2 simulations results : the good one is with the photogenerated current positive (+ Iaa), and the not ok one is the oposite. I also attached the schematic I'm using. The reset voltage is a pulse of 55ns of width at 50ns.

 Could you help me figure out where the problem comes from ?

 Thanks in advance.