Stats

  • Locked Locked
  • Replies 1
  • Subscribers 125
  • Views 14717
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Zoom-in and Zoom-out graphics issues in Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151)

RFStuff

Dear All,

I am facing issues with Virtuso Layout Editor ( IC5141-sub-version 5.10.41.500.6.151) in my machine.
My layout is having a lot of transistors ( like SRAM or DAC) in a small area.
While doing zooming-in or zooming-out of the layout ( i.e. EDIT in place EIP ) of the cell, it becomes slow ( 2 to 3 seconds) for the layout-window to settle to the actual final stage.
This is becoming very painful and irritating while doing the complex layout.


Can anybody please tell why this is happening. How it canbe made faster.

Kind Regards,

  • Maybe your Filter Size  settings have been set too small (Options->Display in the layout editor). If I have it set to the default of 3 (with empty as the style) my small chip layout in 5141 redraws in a fraction of a second. If the filter size is set to 0, then it takes 3-4 seconds. Even with 1 as the filter size it takes less than a second (this means don't attempt to draw anything smaller than a pixel).

    This might also be dependent upon you using some kind of X display tool (e.g. VNC, EoD etc) - I was trying this with a local X server on my Linux laptop.

    Regards,

    Andrew.

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.