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Design rules for library TSMC 0.18U CMOS 018 DEEP (6M, HV FET, S block)

rajrevanth61
Hello all,

Normally the thumb rule followed in the 0.6u technology for the difusion length of an NMOS transistor is 3um+gate length. What is the thumb rule followed for diffusion length in TSMC 0.18u?
I am new to drawing of layouts using the TSMC 0.18U CMOS 018 DEEP (6M, HV FET, S block). previously i had been using 0.6u technology. where can i find the design rules for this TSMC 0.18u.


Please help me.



Thanks in advance

  •  Hi,

    I assume that you simply have a Cadence PDK and not a DRC manual from TSMC.

    Perhaps you can request the manual from TSMC.

    Otherwise you can try looking in the Cadence technology lib.

    The rules that are in the Cadence technology library can be dumped with the Technology File Manager:

    In the CIW: tools-> technology file manager->dump.

    Dump the file and open in a text editor.

    The rule I think you are looking for is "minExtensionDistance" for your diffusion and poly  layers.

    If you don't want to dump the techlib you can also turn on DRD and start drawing some transistors yourself. The rules will be displayed on your cursor:

    In a layout Editor click options-> DRD edit.

    Turn on "notify".

    Then, when you start drawing your transistor, you should see the rule is displayed as soon as you violate the extension rule.

    Hope this helps

     

    Colin

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