CAPTAB DETAILS

Hi auto dipper,

> If we have multiple inputs like in case of CMOS based Nand gate or even bigger circuit then how

> can one calculate the worst case propagation delay?  

 > does the tool support this sort of calculation ?

Andrew's URL will be helpful. I get the impression you are not sure how to compute the "worst case" propagation delay when you have a multiple input logic gate. The propagation delay must be computed for each transition of each input unless the gate is specifically designed to have symmetric delays. Hence, in general if you have a two input gate with two distinct inputs A and B where A and B are not the same, there are eight propagation delay cases to consider:

1. B at logic low and A transitioning from logic high to logic low and logic low to logic high;

2.  B at logic high and A transitioning from logic high to logic low and logic low to logic high;

3. A at logic low and B transitioning from logic high to logic low and logic low to logic high;

4.  A at logic high and B transitioning from logic high to logic low and logic low to logic high;

 Depending on your logic gate, some of these cases may not need to be considered. You can run a transient simulation under your specific environmental condition of interest and compute any of these propagationdelays using the cross() function. I would clip the output signal to start at the time where the input crosses the logic threshold in the direction you are simulating. The difference between the cross() function of the input and output waveforms provides the propagation delay. You will need to determine the maximum propagation delay for each of these cases. If you place each propagation delay in a separate variable, you can use Andrew's suggestion of using the max() function to determine the maximum propagation delay. On the other hane, you may know based on your specific circuit, which propagation delay will be the greatest. 

 Often, in datasheets, the propagation delay is shown as the "average" propagation delay formed by the average of rising to falling and falling to rising propagation delays. Thsi may be fine for a data sheet, but if you need to meet a specific timing constraint, you will need to determine the propagation delay in response to both a rising and falling input and find the maximum.

I hope I understood your intent and my response provides some useful information auto dipper.

Shawn

Hi auto dipper,

> If we have multiple inputs like in case of CMOS based Nand gate or even bigger circuit then how

> can one calculate the worst case propagation delay?  

 > does the tool support this sort of calculation ?

Andrew's URL will be helpful. I get the impression you are not sure how to compute the "worst case" propagation delay when you have a multiple input logic gate. The propagation delay must be computed for each transition of each input unless the gate is specifically designed to have symmetric delays. Hence, in general if you have a two input gate with two distinct inputs A and B where A and B are not the same, there are eight propagation delay cases to consider:

1. B at logic low and A transitioning from logic high to logic low and logic low to logic high;

2.  B at logic high and A transitioning from logic high to logic low and logic low to logic high;

3. A at logic low and B transitioning from logic high to logic low and logic low to logic high;

4.  A at logic high and B transitioning from logic high to logic low and logic low to logic high;

 Depending on your logic gate, some of these cases may not need to be considered. You can run a transient simulation under your specific environmental condition of interest and compute any of these propagationdelays using the cross() function. I would clip the output signal to start at the time where the input crosses the logic threshold in the direction you are simulating. The difference between the cross() function of the input and output waveforms provides the propagation delay. You will need to determine the maximum propagation delay for each of these cases. If you place each propagation delay in a separate variable, you can use Andrew's suggestion of using the max() function to determine the maximum propagation delay. On the other hane, you may know based on your specific circuit, which propagation delay will be the greatest. 

 Often, in datasheets, the propagation delay is shown as the "average" propagation delay formed by the average of rising to falling and falling to rising propagation delays. Thsi may be fine for a data sheet, but if you need to meet a specific timing constraint, you will need to determine the propagation delay in response to both a rising and falling input and find the maximum.

I hope I understood your intent and my response provides some useful information auto dipper.

Shawn