CAPTAB DETAILS

thanks for the reply. 

 If we have multiple inputs like in case of CMOS based Nand gate or even bigger circuit then how can one calculate the worst case propagation delay?  

 does the tool support this sort of calculation ?

 regards

thanks for the reply. 

 If we have multiple inputs like in case of CMOS based Nand gate or even bigger circuit then how can one calculate the worst case propagation delay?  

 does the tool support this sort of calculation ?

 regards

 Dear auto dipper,

> If we have multiple inputs like in case of CMOS based Nand gate or even bigger circuit then how

> can one calculate the worst case propagation delay?  

 I think your question is not a Cadence specific question and is better handled by either you doing the research or thinking or perhaps, if you can not figure it out, posted in a design forum. You will learn the concepts better that way.  I will let Andrew decide if my thought is not proper, but it appears to me to be a circuit analysis question as opposed to a question related to the use of Cadence tools. Cadence provides the cross() function that can be used to compute propagation delays.

Shawn

This post might help - http://www.cadence.com/Community/forums/p/29194/1333616.aspx#1333616

I've no problem with people asking design-related questions here, although forums such as at http://www.designers-guide.org might be better for such things. The Cadence forums don't have to be purely tool related.

Regards,

Andrew. 

 Thanks Shawn and Andrew for the reply.The question is surely related to analysis but specific to Cadence tool. The tool has grown a lot in the past years and it becomes sometimes difficult to keep searching on the internet as to how to use the tool's features aor whether the tool has that feature or not. 

 Hence i posted it here because despite my seraching the spectre manual i feel that many times i don'gt get the proper answer as compared to experience people directing. 

regards

Hi all,

i have an accademic level spice model file for nmos and pmos. I want to include this file in the model library path for simulation purposes. Although i have included it in ADE by Setup-> model libraries but i am still getting the below error after netlist & run -

“ERROR (SFE-23): "input.scs" 39: M0 is an instance of an undefined model equal_vt0”

where equal_vt0.m is the name of the model file.

The model file is attached for reference. Kindly help in perfomring simulation using this model file. The input.scs netlist is also attached. I have used the nmos4 from analog lib in schematic editor and manually given values to device parameter like source area etc..

regards

Hi auto dipper,

> If we have multiple inputs like in case of CMOS based Nand gate or even bigger circuit then how

> can one calculate the worst case propagation delay?  

 > does the tool support this sort of calculation ?

Andrew's URL will be helpful. I get the impression you are not sure how to compute the "worst case" propagation delay when you have a multiple input logic gate. The propagation delay must be computed for each transition of each input unless the gate is specifically designed to have symmetric delays. Hence, in general if you have a two input gate with two distinct inputs A and B where A and B are not the same, there are eight propagation delay cases to consider:

1. B at logic low and A transitioning from logic high to logic low and logic low to logic high;

2.  B at logic high and A transitioning from logic high to logic low and logic low to logic high;

3. A at logic low and B transitioning from logic high to logic low and logic low to logic high;

4.  A at logic high and B transitioning from logic high to logic low and logic low to logic high;

 Depending on your logic gate, some of these cases may not need to be considered. You can run a transient simulation under your specific environmental condition of interest and compute any of these propagationdelays using the cross() function. I would clip the output signal to start at the time where the input crosses the logic threshold in the direction you are simulating. The difference between the cross() function of the input and output waveforms provides the propagation delay. You will need to determine the maximum propagation delay for each of these cases. If you place each propagation delay in a separate variable, you can use Andrew's suggestion of using the max() function to determine the maximum propagation delay. On the other hane, you may know based on your specific circuit, which propagation delay will be the greatest. 

 Often, in datasheets, the propagation delay is shown as the "average" propagation delay formed by the average of rising to falling and falling to rising propagation delays. Thsi may be fine for a data sheet, but if you need to meet a specific timing constraint, you will need to determine the propagation delay in response to both a rising and falling input and find the maximum.

I hope I understood your intent and my response provides some useful information auto dipper.

Shawn

 Dear auto dipper,

Your error message suggests spectre could not find the device instance that refers to the "nmos4" based model. I did not find any errors that suggest spectre was not able to find devices using your "pmos" based model (assuming you are using pmos devices). Have you tried changing your model call to refer to the "nmos" model and not the "nmos4" model? Perhaps the version of the analogLib you are using only contains the "pmos" and "nmos" models and not the "nmos4" model.