• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. How to create layout xl for user defined pcell with same...

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 124
  • Views 12923
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to create layout xl for user defined pcell with same parameters as in schematic??

KarthikJaiho
KarthikJaiho over 11 years ago

 

Hi ,

       I need to create a layout using layout xl. The thing is i need to get the parameters as in schematic for pcells in layout.

Example:-

      nmos has a schematic and layout.  Now i created a pcell with this nmos like nmos_esd with two parameters length and width. And copied nmos schematic and renamed to nmos_esd. 

      But when i tried using "generate all from source" option in layout xl. I am getting corresponding nmos_esd. But the parameters are default and i cant able to edit. Is there any way to map user defined pcell parameters?? Please help..

Thanks & Regards,

 Karthik .

 

  • Cancel
Parents
  • Andrew Beckett
    Andrew Beckett over 11 years ago

    Karthik,

    You shouldn't need to "map parameters" - it should use the same parameters on the schematic as on the layout. My only guess is that your nmos_esd pcell is using different parameters than the CDF parameters used on the original nmos symbol instances.

    The best thing to do would be to contact customer support so that you can share the data - it's very hard to know what you're doing wrong based on the very limited information you've given.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Andrew Beckett
    Andrew Beckett over 11 years ago

    Karthik,

    You shouldn't need to "map parameters" - it should use the same parameters on the schematic as on the layout. My only guess is that your nmos_esd pcell is using different parameters than the CDF parameters used on the original nmos symbol instances.

    The best thing to do would be to contact customer support so that you can share the data - it's very hard to know what you're doing wrong based on the very limited information you've given.

    Regards,

    Andrew.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information