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Sram read operation using switches (SMOD) in pspice

rajrevanth61
Hello all,


Here is my code for SRAM for read operation implemented using switches, can anyone help me where I went wrong in the code, I am gettig both BL and BLB as high when i am trying to read a value of 1, which is stored in Q.

I have initialized the conditions required for the read operation . i.e., I want to read a value of 1 so i have initialized Q as 1 and QR as 0. and for the read operation to take place both the bitlines have been initialized to 1.

Please help me . I am stuck


*source
vdd vdd 0 dc 2

CBL BL 0 1pf
CBLB BLB 0 1pf

*initial conditions stored for read operation
.ic v(Q)=1
.ic v(QR)=0


.ic v(bl)=1
.ic v(blb)=1

*access control
vwl wl 0 pulse(0 2 4m 100u 100u 5m 6m)

*transistors used for latching
sw7 QR 0 Q 0 smod2

sw8 QR vdd Q vdd smod1

sw9 Q 0 QR 0 smod2

sw10 Q vdd QR vdd smod1


*transistors used for data access
sw11 bl Q wl 0 smod2
sw12 blb QR wl 0 smod2

.tran 10m 100m uic
.probe
.MODEL Smod1 VSWITCH(Ron=1000 Roff=1 Von=1V Voff=0.5V)
.MODEL Smod2 VSWITCH(Ron=1 Roff=1000 Von=1V Voff=0.5V)
.end

 i have attached the figureused for writing the netlist.

  • Not really the best forum for questions about pspice, since it's not commonly used for IC design. The PCB Design forum is more likely to have pspice expertise.

    Anyway, I'm not that familiar with pspice (I used it years ago, but not recenty)s, but I quickly looked up VSWITCH in the PSPICE reference guide to confirm what I thought was likely to be the problem.

     

    1. You have the off resistance of the switches as 1Kohm. Given that your bit line capacitors are 1pF, that means the off transisor in conjunction with the bit line capacitors will have a time constant of 1ns. So any isolation you might have had will discharge in a small time compared with the times of your pulse source. With this I doubt the circuit would work. In real life if an SRAM had switches with an off resistance of 1K, you'd be in serious trouble!
    2. You have the on voltage being 1V, and supply voltage and pulse voltage of 2V, but yet have set the initial conditions to be 1V. That means the switches will be partly on - and probably (I didn't try and work it all through) the 1V IC on both bitlines has leaked through to the Q and QR nodes and held everything in some kind of meta-stable state.

     

    I only tried to spot the obvious things.

    BTW, please don't post highlighted text. It's very annoying...

    I suggest you speak to your superviser (I'm guessing you're a university student).

    Andrew. 

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