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a pll stability : phase margin and gain margin ?

Handrian

 Hi,

I designed an pll circuit. I want to check the stabilbity of system in simulation.

- In transient analyses, when I plot the control voltage, its value is constant at 10us, so it's ok !

- In stability analyses, i wanna plot the bode diagram in open loop. So for that, I broke the loop after the divider circuit. I put the Iprobe after the loop fiter. I used the Vsin source with 600mV of amplitude for the input reference.

When i plot with large band the phase margin and the gain phase, I got this graph :

 

It is nothing ! the margin phase and gain phase are not determined.

I don't understand,  What is it due ? may be the method to breal the loop ? Where I put exactly the Iprobe ? What I must enter on the Vsin source ? Did I forget something for the parameter of stability analyses ? 

 

Someone can bring a full method to measure the stability of pll ?

Thanks in advance,

Andrian

Parents

  • Andrian,

    The stb analysis will tell you small-signal stability. That's unlikely to be of any use for a PLL because it will be a large-signal stability problem. Potentially you could use pstb analysis to analyse the stability with the PLL operating, but even that is not necessarily going to tell you whether the loop is stable (it's good for assessing stability of oscillators or for switching amplifiers etc) - it will tell you the "time averaged" stability. The issue with this is that you'd have to be able to run PSS analysis first on your PLL, which requires the PLL to be periodic (i.e. with an integer divide ratio, and ideally not too high a divide ratio because it will be rather memory intensive otherwise).

    You could use stb analysis on a phase-domain model of your PLL, but not on the PLL itself.

    Your picture was missing (note that pictures can't be pasted in (yet - that should come later in the year when we upgrade the forum software); you have to use the Options tab to attach a picture). That said, I don't think that matters because it wouldn't affect my answer.

    Regards,

    Andrew.

Reply

  • Andrian,

    The stb analysis will tell you small-signal stability. That's unlikely to be of any use for a PLL because it will be a large-signal stability problem. Potentially you could use pstb analysis to analyse the stability with the PLL operating, but even that is not necessarily going to tell you whether the loop is stable (it's good for assessing stability of oscillators or for switching amplifiers etc) - it will tell you the "time averaged" stability. The issue with this is that you'd have to be able to run PSS analysis first on your PLL, which requires the PLL to be periodic (i.e. with an integer divide ratio, and ideally not too high a divide ratio because it will be rather memory intensive otherwise).

    You could use stb analysis on a phase-domain model of your PLL, but not on the PLL itself.

    Your picture was missing (note that pictures can't be pasted in (yet - that should come later in the year when we upgrade the forum software); you have to use the Options tab to attach a picture). That said, I don't think that matters because it wouldn't affect my answer.

    Regards,

    Andrew.

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