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Simulation issue with ideal relay implemented in verilog a

lahsivece

 Hi ,

 I am trying to simulate a verilog a relay . Please find the code below (The designer's guide to verilog AMS; Chap 3 listing 13)

`include "constants.vams"
`include "disciplines.vams"

module SWITCH(inp, inn, outp, outn);
input inp,inn;
parameter real switch1=0;
electrical inp, inn, outp, outn;
analog begin
    @(cross(V(inp,inn)-switch1,1))
;
    if(V(inp,inn) > switch1)
        V(outp,outn) <+ 0.0;
    else
    I(outp,outn) <+ 0.0;

end

endmodule

The testbench for simulation and output wavforms are shown below.

If the "switch" waveform (which controls the switch) is switching, shouldn't the output be switching also. Please advise

 

Parents
  • lahsivece

     Hi Andrew,

    That was indeed the case . With a resitor added , relay behaves properly.

    Thanks for pointing this out.

    Regards

    Vishal. 

Reply
  • lahsivece

     Hi Andrew,

    That was indeed the case . With a resitor added , relay behaves properly.

    Thanks for pointing this out.

    Regards

    Vishal. 

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