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  3. DC-DC Converter/ Feedback/ Verilog-A

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DC-DC Converter/ Feedback/ Verilog-A

Pyroblast
Pyroblast over 11 years ago

Hi  dear fellows,

I am trying to design a DC-DC converter using Cadence/Spectre environment.

That said, what I want to do is to measure the feedback loop. I've been told that HSPICE has a simulation option that allows one to break the feedback loop and measure it. The person who told me that didn't knew if the same would be possible with spectre.

After searching around the web, I found a website where they were talking about the stb analysis. From what I've understood and read on the spectre manual this stb analysis allow:

"The loop-based and device-based algorithms are available in the Spectre circuit simulator for small-signal stability analysis. Both are based on the calculation of Bode’s return ratio. The analysis output are loop gain waveform, gain margin, and phase margin."

"Linearizes the circuit about the DC operating point and computes loop gain, gain margin, and phase margin for a specific feedback loop or an active device. The stability of the circuit can be determined from the loop gain waveform. The probe parameter must be specified to perform stability analysis."

On that website they did this analysis with a Single-ended Opamp simulation. To perform this analysis, a iprobe component was needed.

I haven't tried this yet.

 So what I'd like to ask is if someone here as used this kind of analysis and if it was successful.

Based on this, I was wondering if it is possible to do the same thing but in a feedback loop of a dc-dc converter? Break it on a particular part, block th AC signal and let the DC pass.

Taking the advantage of this post, I'd like to as anoter thing.

I don't know if some of you guys that are reading this post are familiar with DC-DC Converter. Picking the Basso's book, where he teaches how to simulate DC-DC Converters using PSPICE, he uses a switch model to model the power devices. He uses a transformer, current sources, etc.

It is possible to implement such models in Cadence? Transformers, current sources, etc.

Please feel free to comment, give an opinion, share experiences. If you can give some tips too I would appreciate.

Sorry for the long post.

Kind regards

 

EDIT: Can someone tell me where can I find some good Verilog-A models for comparator, ramp generator, PWM, etc?

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  • Frank Wiedmann
    Frank Wiedmann over 11 years ago
    I suggest that you put your PAC source at a node of your circuit where you have an unmodulated signal. This would mean that you include the circuit that converts a DC voltage to the duty cycle of the converter. Put a DC source with the correct voltage at its input and set its PAC magnitude to 1. Make sure that in your netlist, the PSS analysis appears before the PAC analysis; it seems like you had an error in your simulation setup.
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  • Frank Wiedmann
    Frank Wiedmann over 11 years ago
    I suggest that you put your PAC source at a node of your circuit where you have an unmodulated signal. This would mean that you include the circuit that converts a DC voltage to the duty cycle of the converter. Put a DC source with the correct voltage at its input and set its PAC magnitude to 1. Make sure that in your netlist, the PSS analysis appears before the PAC analysis; it seems like you had an error in your simulation setup.
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