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DC-DC Converter/ Feedback/ Verilog-A

Pyroblast

Hi  dear fellows,

I am trying to design a DC-DC converter using Cadence/Spectre environment.

That said, what I want to do is to measure the feedback loop. I've been told that HSPICE has a simulation option that allows one to break the feedback loop and measure it. The person who told me that didn't knew if the same would be possible with spectre.

After searching around the web, I found a website where they were talking about the stb analysis. From what I've understood and read on the spectre manual this stb analysis allow:

"The loop-based and device-based algorithms are available in the Spectre circuit simulator for small-signal stability analysis. Both are based on the calculation of Bode’s return ratio. The analysis output are loop gain waveform, gain margin, and phase margin."

"Linearizes the circuit about the DC operating point and computes loop gain, gain margin, and phase margin for a specific feedback loop or an active device. The stability of the circuit can be determined from the loop gain waveform. The probe parameter must be specified to perform stability analysis."

On that website they did this analysis with a Single-ended Opamp simulation. To perform this analysis, a iprobe component was needed.

I haven't tried this yet.

 So what I'd like to ask is if someone here as used this kind of analysis and if it was successful.

Based on this, I was wondering if it is possible to do the same thing but in a feedback loop of a dc-dc converter? Break it on a particular part, block th AC signal and let the DC pass.

Taking the advantage of this post, I'd like to as anoter thing.

I don't know if some of you guys that are reading this post are familiar with DC-DC Converter. Picking the Basso's book, where he teaches how to simulate DC-DC Converters using PSPICE, he uses a switch model to model the power devices. He uses a transformer, current sources, etc.

It is possible to implement such models in Cadence? Transformers, current sources, etc.

Please feel free to comment, give an opinion, share experiences. If you can give some tips too I would appreciate.

Sorry for the long post.

Kind regards

 

EDIT: Can someone tell me where can I find some good Verilog-A models for comparator, ramp generator, PWM, etc?

Parents
  • Pyroblast

    Hi Frank,

    I have simulated the circuit using a PWM block. The PWM block that I used, was built using a VCVS, a VPULSE with the parameters set to get a sawtooth waveform as close to reality as possible and a VDC source. At the output I got a nice squared waveform.

    You can see the circuit here:

    (the schematic is pretty much the same as the other one I have posted, but instead of using the VPULSE to simulate the PWM, I use now the VCVS as described above).

    and the waveforms:

     

    In the next pictures I present the configurations that I used to perform the analysis:

    The VCVS:

    The VPULSE configured to get the an aproximate sawtooth waveform:

    The VDC configuration, which was used at same time as an AC Source, provided the fact that the VDC has a PAC Magnitude field:

    The PAC Analysis configuration:

     

    After this, I asked for the direct plot and selected the PAC Analysis:

    When I choose PAC analysis, (by intuition, because I never used PAC analysis) I selected the Function: Voltage, Sweep: Spectrum, Modifier: dB20. With all this selected a message appears below the "Add To Outputs", freqaxis = absout; > Select Net on schematic.

    Well, I select the Vout net. The plot that I get is something like this:

    (using the "sweep type" linear)

    and this:

    (using the "sweep type" logarithm, with 30 points per decade) 

    I think that this has nothing to do with the open loop frequency response of the converter, because it doesn't look like the typical frequency response of the converter in open loop (it looks more like the frequency response of an OPAMP, even though the gain is not so high) - this taking into account some results that we can find through the web, like for example here: http://ecee.colorado.edu/~ecen5807/course_material/MATLAB/MATLAB_Simulink_introduction.pdf in page 18, or even though the presentation that you have posted here. I can't find that "peak" on the frequency response, but maybe it might be related to the losses in the circuit or maybe because of my operating frequency, 500MHz?

    NOTES: I tried to select other nets on the schematic (just to test) but I didn't got any interesting result.

    Besides that, I tried to get the frequency response selecting the other existing options, like the Voltage Gain (numerator I selected the Vout net and the denominator I selected the net where I have the VDC source connected to the VCVS), but nothing special happened.

     

    Can you give me any clue? What I am doing wrong? I think I did as you told me (at least it was as I have interpreted):

    "I suggest that you put your PAC source at a node of your circuit where you have an unmodulated signal. (I presume that is at the VDC source) This would mean that you include the circuit that converts a DC voltage to the duty cycle of the converter. (It was what I did, I used the VCVS with the VDC @ the - terminal, the duty-cycle is the output of the VCVS). Put a DC source with the correct voltage at its input and set its PAC magnitude to 1 (It was what I did, as you can see in the picture above - vdc_config). Make sure that in your netlist, the PSS analysis appears before the PAC analysis; it seems like you had an error in your simulation setup."

     

    I am really looking forward for your reply. Thank you in advance.

     

    Kind regards. 

     

Reply
  • Pyroblast

    Hi Frank,

    I have simulated the circuit using a PWM block. The PWM block that I used, was built using a VCVS, a VPULSE with the parameters set to get a sawtooth waveform as close to reality as possible and a VDC source. At the output I got a nice squared waveform.

    You can see the circuit here:

    (the schematic is pretty much the same as the other one I have posted, but instead of using the VPULSE to simulate the PWM, I use now the VCVS as described above).

    and the waveforms:

     

    In the next pictures I present the configurations that I used to perform the analysis:

    The VCVS:

    The VPULSE configured to get the an aproximate sawtooth waveform:

    The VDC configuration, which was used at same time as an AC Source, provided the fact that the VDC has a PAC Magnitude field:

    The PAC Analysis configuration:

     

    After this, I asked for the direct plot and selected the PAC Analysis:

    When I choose PAC analysis, (by intuition, because I never used PAC analysis) I selected the Function: Voltage, Sweep: Spectrum, Modifier: dB20. With all this selected a message appears below the "Add To Outputs", freqaxis = absout; > Select Net on schematic.

    Well, I select the Vout net. The plot that I get is something like this:

    (using the "sweep type" linear)

    and this:

    (using the "sweep type" logarithm, with 30 points per decade) 

    I think that this has nothing to do with the open loop frequency response of the converter, because it doesn't look like the typical frequency response of the converter in open loop (it looks more like the frequency response of an OPAMP, even though the gain is not so high) - this taking into account some results that we can find through the web, like for example here: http://ecee.colorado.edu/~ecen5807/course_material/MATLAB/MATLAB_Simulink_introduction.pdf in page 18, or even though the presentation that you have posted here. I can't find that "peak" on the frequency response, but maybe it might be related to the losses in the circuit or maybe because of my operating frequency, 500MHz?

    NOTES: I tried to select other nets on the schematic (just to test) but I didn't got any interesting result.

    Besides that, I tried to get the frequency response selecting the other existing options, like the Voltage Gain (numerator I selected the Vout net and the denominator I selected the net where I have the VDC source connected to the VCVS), but nothing special happened.

     

    Can you give me any clue? What I am doing wrong? I think I did as you told me (at least it was as I have interpreted):

    "I suggest that you put your PAC source at a node of your circuit where you have an unmodulated signal. (I presume that is at the VDC source) This would mean that you include the circuit that converts a DC voltage to the duty cycle of the converter. (It was what I did, I used the VCVS with the VDC @ the - terminal, the duty-cycle is the output of the VCVS). Put a DC source with the correct voltage at its input and set its PAC magnitude to 1 (It was what I did, as you can see in the picture above - vdc_config). Make sure that in your netlist, the PSS analysis appears before the PAC analysis; it seems like you had an error in your simulation setup."

     

    I am really looking forward for your reply. Thank you in advance.

     

    Kind regards. 

     

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