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DC-DC Converter/ Feedback/ Verilog-A

Pyroblast

Hi  dear fellows,

I am trying to design a DC-DC converter using Cadence/Spectre environment.

That said, what I want to do is to measure the feedback loop. I've been told that HSPICE has a simulation option that allows one to break the feedback loop and measure it. The person who told me that didn't knew if the same would be possible with spectre.

After searching around the web, I found a website where they were talking about the stb analysis. From what I've understood and read on the spectre manual this stb analysis allow:

"The loop-based and device-based algorithms are available in the Spectre circuit simulator for small-signal stability analysis. Both are based on the calculation of Bode’s return ratio. The analysis output are loop gain waveform, gain margin, and phase margin."

"Linearizes the circuit about the DC operating point and computes loop gain, gain margin, and phase margin for a specific feedback loop or an active device. The stability of the circuit can be determined from the loop gain waveform. The probe parameter must be specified to perform stability analysis."

On that website they did this analysis with a Single-ended Opamp simulation. To perform this analysis, a iprobe component was needed.

I haven't tried this yet.

 So what I'd like to ask is if someone here as used this kind of analysis and if it was successful.

Based on this, I was wondering if it is possible to do the same thing but in a feedback loop of a dc-dc converter? Break it on a particular part, block th AC signal and let the DC pass.

Taking the advantage of this post, I'd like to as anoter thing.

I don't know if some of you guys that are reading this post are familiar with DC-DC Converter. Picking the Basso's book, where he teaches how to simulate DC-DC Converters using PSPICE, he uses a switch model to model the power devices. He uses a transformer, current sources, etc.

It is possible to implement such models in Cadence? Transformers, current sources, etc.

Please feel free to comment, give an opinion, share experiences. If you can give some tips too I would appreciate.

Sorry for the long post.

Kind regards

 

EDIT: Can someone tell me where can I find some good Verilog-A models for comparator, ramp generator, PWM, etc?

Parents
  • Pyroblast

    Hi there Frank,

    Yes, I came up with this idea after I had some problems with that "hidden state" detail. Because I don't have much experience (I would say none) with VerilogA I decided to do that with the VCVS. I was planning to construct the feedback loop main blocks through VerilogA (at least the comparator, an OPAMP, etc) but because of this issue I will try to do everything with VCVS (I will have to do some research if this is possible - Does anyone knows if it is possible?)

    So all the configurations that I have done and the PAC Source positioning are correct? Is that it? (even though you have said that you believe that the setup is correct) Question: 1) Is there anyway that I could confirm this through another method? For example MATLAB and see if the results are the same? 2) Is there any problem for this purpose, use the PAC Magnitude field on the VDC SOURCE to perform the PAC Analysi? 3) In this case, the frequency response that I am seeing is the converter + pwm modulator (that 1/Vm model for the PWM). Is it?

    Now, can I do the same thing, perform the PAC Analysis but now inserting "the PAC source" on the Power Supply to see the frequency response from the output to the input? I don't know if make sense to ask this plot, because, from what I have read, the transfer function that we need to design the controller is the Vout(s)/d(s).

    I have done a similar experience using a LC filter and the configuration with VCVS + VDC Source + Vpulse configured to get a sawtooth based on a application note and I got similar results.

    The circuit:

    Frequency response:

    I used the pretty same configurations.

    EDIT: The red response is with the resistor modeling the inductor and capacitor internal resistance and the green one is wth the resistors equal to zero (no losses). Allow me to ask you a question regarding this: If you notice, the gain of the filter is above 0dB while, if you look here: http://www.ti.com/lit/an/slva301/slva301.pdf at page 10 & 11 you'll see the filter I am talking about. There you can see that the gain is on 0dB. What might causing this discrepancy? Maybe because I am using a Square wave at the input? If so, How can I put a sinusoidal input while preserving that VDC node (unmodulated) to perform the PAC Analysis? Or I can use directly the VSIN and perform the PSS + PAC analysis?

    Another detail is that I have simulated the LC filter from the buck converter in the same fashion that I did with above mentioned one and there I got a slight "peak". In this case there are no RDS(on) from the MOSFETs.

     

    I forgot to post here the frequency response of the converter magnitude in dB and phase:

     

    A curious thing is that the phase plot @ the crossover frequency has a positive value. Should not be negative? I did the same with the filter I post above and I got this:

    The same result in the sense that the phase has a positive value. Should not be negative too?

    Kind regards and thank you so much for your availability Frank.

Reply
  • Pyroblast

    Hi there Frank,

    Yes, I came up with this idea after I had some problems with that "hidden state" detail. Because I don't have much experience (I would say none) with VerilogA I decided to do that with the VCVS. I was planning to construct the feedback loop main blocks through VerilogA (at least the comparator, an OPAMP, etc) but because of this issue I will try to do everything with VCVS (I will have to do some research if this is possible - Does anyone knows if it is possible?)

    So all the configurations that I have done and the PAC Source positioning are correct? Is that it? (even though you have said that you believe that the setup is correct) Question: 1) Is there anyway that I could confirm this through another method? For example MATLAB and see if the results are the same? 2) Is there any problem for this purpose, use the PAC Magnitude field on the VDC SOURCE to perform the PAC Analysi? 3) In this case, the frequency response that I am seeing is the converter + pwm modulator (that 1/Vm model for the PWM). Is it?

    Now, can I do the same thing, perform the PAC Analysis but now inserting "the PAC source" on the Power Supply to see the frequency response from the output to the input? I don't know if make sense to ask this plot, because, from what I have read, the transfer function that we need to design the controller is the Vout(s)/d(s).

    I have done a similar experience using a LC filter and the configuration with VCVS + VDC Source + Vpulse configured to get a sawtooth based on a application note and I got similar results.

    The circuit:

    Frequency response:

    I used the pretty same configurations.

    EDIT: The red response is with the resistor modeling the inductor and capacitor internal resistance and the green one is wth the resistors equal to zero (no losses). Allow me to ask you a question regarding this: If you notice, the gain of the filter is above 0dB while, if you look here: http://www.ti.com/lit/an/slva301/slva301.pdf at page 10 & 11 you'll see the filter I am talking about. There you can see that the gain is on 0dB. What might causing this discrepancy? Maybe because I am using a Square wave at the input? If so, How can I put a sinusoidal input while preserving that VDC node (unmodulated) to perform the PAC Analysis? Or I can use directly the VSIN and perform the PSS + PAC analysis?

    Another detail is that I have simulated the LC filter from the buck converter in the same fashion that I did with above mentioned one and there I got a slight "peak". In this case there are no RDS(on) from the MOSFETs.

     

    I forgot to post here the frequency response of the converter magnitude in dB and phase:

     

    A curious thing is that the phase plot @ the crossover frequency has a positive value. Should not be negative? I did the same with the filter I post above and I got this:

    The same result in the sense that the phase has a positive value. Should not be negative too?

    Kind regards and thank you so much for your availability Frank.

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