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DC-DC Converter/ Feedback/ Verilog-A

Pyroblast

Hi  dear fellows,

I am trying to design a DC-DC converter using Cadence/Spectre environment.

That said, what I want to do is to measure the feedback loop. I've been told that HSPICE has a simulation option that allows one to break the feedback loop and measure it. The person who told me that didn't knew if the same would be possible with spectre.

After searching around the web, I found a website where they were talking about the stb analysis. From what I've understood and read on the spectre manual this stb analysis allow:

"The loop-based and device-based algorithms are available in the Spectre circuit simulator for small-signal stability analysis. Both are based on the calculation of Bode’s return ratio. The analysis output are loop gain waveform, gain margin, and phase margin."

"Linearizes the circuit about the DC operating point and computes loop gain, gain margin, and phase margin for a specific feedback loop or an active device. The stability of the circuit can be determined from the loop gain waveform. The probe parameter must be specified to perform stability analysis."

On that website they did this analysis with a Single-ended Opamp simulation. To perform this analysis, a iprobe component was needed.

I haven't tried this yet.

 So what I'd like to ask is if someone here as used this kind of analysis and if it was successful.

Based on this, I was wondering if it is possible to do the same thing but in a feedback loop of a dc-dc converter? Break it on a particular part, block th AC signal and let the DC pass.

Taking the advantage of this post, I'd like to as anoter thing.

I don't know if some of you guys that are reading this post are familiar with DC-DC Converter. Picking the Basso's book, where he teaches how to simulate DC-DC Converters using PSPICE, he uses a switch model to model the power devices. He uses a transformer, current sources, etc.

It is possible to implement such models in Cadence? Transformers, current sources, etc.

Please feel free to comment, give an opinion, share experiences. If you can give some tips too I would appreciate.

Sorry for the long post.

Kind regards

 

EDIT: Can someone tell me where can I find some good Verilog-A models for comparator, ramp generator, PWM, etc?

Parents
  • Pyroblast

    Hi Frank,

    Regarding the DC gain, what I did was: find the linear unities from the 7.67dB, which corresponds to 2.418.

    Then I increased the value of the VDC source, from 500mV to 510mV.

    The output voltage @ 500mV was varying from 1.251V to 1.2799V which corresponds to  28.9mV of riple. I found the mean value: 1.265V;

    The output voltage @ 510mV was varying from 1.227V to 1.255V which corresponds to 28mV of ripple. I found the mean value: 1.241V;

     

    If we multiply the linear unities of the gain (2.418) by the 10mV increase that gives 24.18mV.

    If we subtract the obtained voltages for the 10mV increase on the VDC source, we get  24mV.

    Is this what you were saying?

    However, there is an issue here: If we are incresing the VDC source what we are doing is reducing the duty cycle, so of course the output voltage would be lower. In this case we can analyze the DC gain in this fashion? Regarding that if we have a DC gain we would have an increase on the signal output. I don't know if I made myself clear.

    For the case at higher frequencies, I must insert a VSIN source in series with the VDC source (that is located at the "minus" signal of the VCVS)? Is that it?

    Concerning the filter, I remembered that and I got the same results when simulating with a VSIN at the input of the filter. However I didn't understood well those 5kHz that in the application note from TI they refer. They say that the cut-off frequency is around 5KHz. From what I know the cut-off frequency is measured 3 dB bellow the DC gain (right?) and in my case I get 7.5KHz.

    That suggestion that you gave me I will give it a try later. I will try to setup the same circuit that is presented on that article and see if I can get the same results. I'll let you know.

    "Why do you think that the phase at the crossover frequency of the transfer functions you plotted should be negative? You will have to design the feedback circuit in such a way that the loop gain satisfies the conditions for stability."

    Well, I said that because it was something that I found to be common in all the frequency responses I saw around the web and books. Maybe the switching frequency has here some influence, since all that converters are operating at a very low frequency compared to mine.

    Thank again for your patience.

    I am looking forward for your reply.

    Kind regards.

Reply
  • Pyroblast

    Hi Frank,

    Regarding the DC gain, what I did was: find the linear unities from the 7.67dB, which corresponds to 2.418.

    Then I increased the value of the VDC source, from 500mV to 510mV.

    The output voltage @ 500mV was varying from 1.251V to 1.2799V which corresponds to  28.9mV of riple. I found the mean value: 1.265V;

    The output voltage @ 510mV was varying from 1.227V to 1.255V which corresponds to 28mV of ripple. I found the mean value: 1.241V;

     

    If we multiply the linear unities of the gain (2.418) by the 10mV increase that gives 24.18mV.

    If we subtract the obtained voltages for the 10mV increase on the VDC source, we get  24mV.

    Is this what you were saying?

    However, there is an issue here: If we are incresing the VDC source what we are doing is reducing the duty cycle, so of course the output voltage would be lower. In this case we can analyze the DC gain in this fashion? Regarding that if we have a DC gain we would have an increase on the signal output. I don't know if I made myself clear.

    For the case at higher frequencies, I must insert a VSIN source in series with the VDC source (that is located at the "minus" signal of the VCVS)? Is that it?

    Concerning the filter, I remembered that and I got the same results when simulating with a VSIN at the input of the filter. However I didn't understood well those 5kHz that in the application note from TI they refer. They say that the cut-off frequency is around 5KHz. From what I know the cut-off frequency is measured 3 dB bellow the DC gain (right?) and in my case I get 7.5KHz.

    That suggestion that you gave me I will give it a try later. I will try to setup the same circuit that is presented on that article and see if I can get the same results. I'll let you know.

    "Why do you think that the phase at the crossover frequency of the transfer functions you plotted should be negative? You will have to design the feedback circuit in such a way that the loop gain satisfies the conditions for stability."

    Well, I said that because it was something that I found to be common in all the frequency responses I saw around the web and books. Maybe the switching frequency has here some influence, since all that converters are operating at a very low frequency compared to mine.

    Thank again for your patience.

    I am looking forward for your reply.

    Kind regards.

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