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DC-DC Converter/ Feedback/ Verilog-A

Pyroblast

Hi  dear fellows,

I am trying to design a DC-DC converter using Cadence/Spectre environment.

That said, what I want to do is to measure the feedback loop. I've been told that HSPICE has a simulation option that allows one to break the feedback loop and measure it. The person who told me that didn't knew if the same would be possible with spectre.

After searching around the web, I found a website where they were talking about the stb analysis. From what I've understood and read on the spectre manual this stb analysis allow:

"The loop-based and device-based algorithms are available in the Spectre circuit simulator for small-signal stability analysis. Both are based on the calculation of Bode’s return ratio. The analysis output are loop gain waveform, gain margin, and phase margin."

"Linearizes the circuit about the DC operating point and computes loop gain, gain margin, and phase margin for a specific feedback loop or an active device. The stability of the circuit can be determined from the loop gain waveform. The probe parameter must be specified to perform stability analysis."

On that website they did this analysis with a Single-ended Opamp simulation. To perform this analysis, a iprobe component was needed.

I haven't tried this yet.

 So what I'd like to ask is if someone here as used this kind of analysis and if it was successful.

Based on this, I was wondering if it is possible to do the same thing but in a feedback loop of a dc-dc converter? Break it on a particular part, block th AC signal and let the DC pass.

Taking the advantage of this post, I'd like to as anoter thing.

I don't know if some of you guys that are reading this post are familiar with DC-DC Converter. Picking the Basso's book, where he teaches how to simulate DC-DC Converters using PSPICE, he uses a switch model to model the power devices. He uses a transformer, current sources, etc.

It is possible to implement such models in Cadence? Transformers, current sources, etc.

Please feel free to comment, give an opinion, share experiences. If you can give some tips too I would appreciate.

Sorry for the long post.

Kind regards

 

EDIT: Can someone tell me where can I find some good Verilog-A models for comparator, ramp generator, PWM, etc?

Parents
  • Pyroblast

    Frank, regarding the insetion of the VSIN source in series with the VDC source (or the replacement that you talked about) I tried to simulate this using the transient analysis and at the output I got the output voltage modulated, as you can see bellow:

    To be honest I don't know what this information means.

    I used an amplitude of 100mV and a frequency os 100MHz (this was chosen randomly).What concerns to the amplitude, the output modulated signal has a lower value. About the phase, well, they seem to be in phase, right? What can we conclude from here?

    What we are doing here remembers me the way that inverters work, to produce that 50Hz output frequency.

    Nothing comes into my mind regatding that 180 degree @ DC!

    Kind regards.

    EDIT: Frank I tried to simulate the circuit from this website: http://edn.com/design/analog/4327245/Periodic-steady-state-and-small-signal-analyses-of-switching-regulators but without success.

    First I was doing a mistake, I was using a simple PMOS and DIODE from the analogLib. After a spectre error referring to the model I discovered that the author of the article maybe had is own PMOS and DIODE model/parameters and he didn't posted that in the article. He has this:

    // PMOS model

    include "cmos_definition.scs" 

    Even though there is nothing related to the DIODE maybe he has that diode model insed that file. He has the model name as DIODEideal. However, from what I have searched, I found that we need to put the model name in the analogLib PMOS transistor which appears within the schematic symbol, that in this case he has PMOS, but the name where he have the model is cmos_definition.scs.

    Whatever. I used a PMOS from my tech lib. With the same dimension.

    After replacing that PMOS I ran a simulation and an error appeared again. Now was the diode. I used a tech lib DIODE. I set the DIODE L and W to 25u than used a multiplier of 5.

    The schematic that I used was the same as the author but without the error amplifier, the comparator from the PWM, and all that passive components.  Instead of those I used that setup with the VCVS. Another change that I did was the power supply voltage, I used 3.3V. The sawtooth generator I have setup exactly the same as he has in the netlist and from what we can see on the PSS analysis plot, he has the control voltage around 1V, that was what I used too in my VDC source in the VCVS.

    After running a simulation PSS, PAC and TRAN I ploted the Vout (PSS) and I had an output voltage around 200mV which is very low. Tried to plot the frequency response and it was a bit different, starting from the gain value, which was very lower (-25dB), of course.

    I don't know if this problem might be related to the way the signal is presented to the PMOS gate (through the VCVS). 

    I am out of any ideas.

    Can you give a type or so? 

Reply
  • Pyroblast

    Frank, regarding the insetion of the VSIN source in series with the VDC source (or the replacement that you talked about) I tried to simulate this using the transient analysis and at the output I got the output voltage modulated, as you can see bellow:

    To be honest I don't know what this information means.

    I used an amplitude of 100mV and a frequency os 100MHz (this was chosen randomly).What concerns to the amplitude, the output modulated signal has a lower value. About the phase, well, they seem to be in phase, right? What can we conclude from here?

    What we are doing here remembers me the way that inverters work, to produce that 50Hz output frequency.

    Nothing comes into my mind regatding that 180 degree @ DC!

    Kind regards.

    EDIT: Frank I tried to simulate the circuit from this website: http://edn.com/design/analog/4327245/Periodic-steady-state-and-small-signal-analyses-of-switching-regulators but without success.

    First I was doing a mistake, I was using a simple PMOS and DIODE from the analogLib. After a spectre error referring to the model I discovered that the author of the article maybe had is own PMOS and DIODE model/parameters and he didn't posted that in the article. He has this:

    // PMOS model

    include "cmos_definition.scs" 

    Even though there is nothing related to the DIODE maybe he has that diode model insed that file. He has the model name as DIODEideal. However, from what I have searched, I found that we need to put the model name in the analogLib PMOS transistor which appears within the schematic symbol, that in this case he has PMOS, but the name where he have the model is cmos_definition.scs.

    Whatever. I used a PMOS from my tech lib. With the same dimension.

    After replacing that PMOS I ran a simulation and an error appeared again. Now was the diode. I used a tech lib DIODE. I set the DIODE L and W to 25u than used a multiplier of 5.

    The schematic that I used was the same as the author but without the error amplifier, the comparator from the PWM, and all that passive components.  Instead of those I used that setup with the VCVS. Another change that I did was the power supply voltage, I used 3.3V. The sawtooth generator I have setup exactly the same as he has in the netlist and from what we can see on the PSS analysis plot, he has the control voltage around 1V, that was what I used too in my VDC source in the VCVS.

    After running a simulation PSS, PAC and TRAN I ploted the Vout (PSS) and I had an output voltage around 200mV which is very low. Tried to plot the frequency response and it was a bit different, starting from the gain value, which was very lower (-25dB), of course.

    I don't know if this problem might be related to the way the signal is presented to the PMOS gate (through the VCVS). 

    I am out of any ideas.

    Can you give a type or so? 

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