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DC-DC Converter/ Feedback/ Verilog-A

Pyroblast

Hi  dear fellows,

I am trying to design a DC-DC converter using Cadence/Spectre environment.

That said, what I want to do is to measure the feedback loop. I've been told that HSPICE has a simulation option that allows one to break the feedback loop and measure it. The person who told me that didn't knew if the same would be possible with spectre.

After searching around the web, I found a website where they were talking about the stb analysis. From what I've understood and read on the spectre manual this stb analysis allow:

"The loop-based and device-based algorithms are available in the Spectre circuit simulator for small-signal stability analysis. Both are based on the calculation of Bode’s return ratio. The analysis output are loop gain waveform, gain margin, and phase margin."

"Linearizes the circuit about the DC operating point and computes loop gain, gain margin, and phase margin for a specific feedback loop or an active device. The stability of the circuit can be determined from the loop gain waveform. The probe parameter must be specified to perform stability analysis."

On that website they did this analysis with a Single-ended Opamp simulation. To perform this analysis, a iprobe component was needed.

I haven't tried this yet.

 So what I'd like to ask is if someone here as used this kind of analysis and if it was successful.

Based on this, I was wondering if it is possible to do the same thing but in a feedback loop of a dc-dc converter? Break it on a particular part, block th AC signal and let the DC pass.

Taking the advantage of this post, I'd like to as anoter thing.

I don't know if some of you guys that are reading this post are familiar with DC-DC Converter. Picking the Basso's book, where he teaches how to simulate DC-DC Converters using PSPICE, he uses a switch model to model the power devices. He uses a transformer, current sources, etc.

It is possible to implement such models in Cadence? Transformers, current sources, etc.

Please feel free to comment, give an opinion, share experiences. If you can give some tips too I would appreciate.

Sorry for the long post.

Kind regards

 

EDIT: Can someone tell me where can I find some good Verilog-A models for comparator, ramp generator, PWM, etc?

  • Pyroblast

     Frank I have tried everything on trying to implement a similar circuit like the one there is at the EDN website. I am out of ideas.

  • Frank Wiedmann

    Well, a phase of 180 degrees at DC means that your linear gain at DC is not +2.418 but -2.418. This means that if you increase the input voltage by 10 mV, the output voltage will not increase but decrease by 24.18 mV, just as you have observed.

    Your simulation with the VSIN source shows a phase of approximately 0 degrees and a linear gain of a little less than 0.7 (you should use an imagined sinusoidal centerline of the small ripple when you place the markers H1 and H2). What do you get at 100 MHz in a PAC analysis? (You will have to turn off the sine for the PAC analysis.) If there is some difference between the results, it might be because 100 mV is probably already a little too large for the linear approximation of the PAC analysis.

    It's a bit unfortunate that the EDN example does not include the models, which makes it a little difficult to reproduce. As you don't seem to simulate the entire circuit, I am not very surprised that you are getting different results (the results shown represent the loop gain for the entire circuit). However, as long as you can successfully simulate your own circuit, it's probably not a big problem if you cannot reproduce the results in this example. I was just proposing this at an additional testcase for your simulation setup. 

  • Pyroblast

    Hi Frank,

    Regarding the question you did, about what I get at 100MHz in a PAC analysis, I didn't understood. You want me to simulate @ 100MHz instead of 500MHz? The VSIN source is the one that is operating at 100MHz. If you are sayin that I need to turn off the sine for the PAC analysis, how can I see what PAC analysis gives me turning off the sine?

    About the " (you should use an imagined sinusoidal centerline of the small ripple when you place the markers H1 and H2)", I thought that what we should measure was the amplitude variation of the sine. I put 200mV amplitude @ input and I got at the output a (1.34413 - 1.20597) = 138.2mV which gives a 138.2/200 = aprox. 0.7, has you said. What would worthto take the centeline of the small ripple at the output?

     

  • Frank Wiedmann

    I want you to read out the value at 100 MHz in your plot http://postimg.org/image/f4rzrjzx1/ (if this simulation was done with the same circuit as your recent one). In this simulation, there was no 100 MHz sine, remember?

    When you were reading out the DC values at the output, you were taking the mean value of the ripple, remember? So you should do something similar for the sine. You seem to have placed your markers H1 and H2 at the extrema of the ripple.

  • Pyroblast

    Hi frank, if everything is ok, those should be the values at 100MHz:

    If you think that the result is not consistent with the previous one, I can simulated everything again.

    Frank, intrinsically the converter it is stable, correct? He has a fase margim around 37 degrees. When adding thecontroller, that phase margin will be affected. Now, allow me to ask you a question: Why we need the contro-to-output transfer function do design the controller?

    Kind regards.

    EDIT: Just for curiosity, why you asked for that particular point?

  • Frank Wiedmann

    Well, of course because I want to compare the result of your TRAN analysis with the VSIN source at 100 MHz with the result of your PAC analysis. The phase seems to match pretty well: the TRAN analysis gives approximately 0 degrees and the PAC analysis gives 3.8 degrees. The amplitude does not match quite as well: the TRAN analysis gives approximately 0.7 and the PAC analysis gives -5.63 dB, corresponding to a linear value of 0.52. This could either be because you did not simulate exactly the same circuit in both cases or because the amplitude of 100 mV in the TRAN analysis is already too large for the linear approximation of the PAC analysis. To get a better understanding of the relationship between TRAN analysis and AC analysis, I suggest that you take a look at http://cmosedu.com/videos/ltspice/CMOSedu_SPICE_Ch_1.pdf.

    If you close the loop in such a way that the transfer function shown here becomes your loop gain, your converter will be stable. However, there will be some ringing in the step response due to the rather small phase margin. There will also be some DC error due to the rather small loop gain at DC. See for example pages 21 and 31 of http://www.onsemi.com/pub_link/Collateral/TND352-D.PDF.

  • Pyroblast

    Frank thanks for the reply. I can do a new simulation to assess this issue, however, I have now designed the compensator using VCVS as ideal OPAMP and have closed the loop.

  • Pyroblast

    I don't know if I am doing something wrong.

     

     

  • Pyroblast

    Hi again. I am stuck on this last simulation.

     

     

     

  • nnlt

    hi dear pyroblast,

    do you have the dcdc veriloga model? can you share whit us?  i try to write the dcdc power state model with veriloga, but i fail.

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