DC-DC Converter/ Feedback/ Verilog-A

Well Frank, I would say that we would have a wierd result and the frequency response probably wouldn't be what I are expecting. We'd have an amplitude modulated signal. Right? (Maybe we may think on the fourier transform of a pulse shaped waveform (squarewave))

So, once done with the modulator block (PWM), I should use the PAC Magnitude field on the VDC SOURCE, connected to the input of the comparator (negative terminal - error voltage) and the sawtooth waveform to the positive one?

Thank you so much Frank.

I'll give some news later.

Regards.

Hi Frank,

I have simulated the circuit using a PWM block. The PWM block that I used, was built using a VCVS, a VPULSE with the parameters set to get a sawtooth waveform as close to reality as possible and a VDC source. At the output I got a nice squared waveform.

You can see the circuit here:

(the schematic is pretty much the same as the other one I have posted, but instead of using the VPULSE to simulate the PWM, I use now the VCVS as described above).

and the waveforms:

In the next pictures I present the configurations that I used to perform the analysis:

The VCVS:

The VPULSE configured to get the an aproximate sawtooth waveform:

The VDC configuration, which was used at same time as an AC Source, provided the fact that the VDC has a PAC Magnitude field:

The PAC Analysis configuration:

After this, I asked for the direct plot and selected the PAC Analysis:

When I choose PAC analysis, (by intuition, because I never used PAC analysis) I selected the Function: Voltage, Sweep: Spectrum, Modifier: dB20. With all this selected a message appears below the "Add To Outputs", freqaxis = absout; > Select Net on schematic.

Well, I select the Vout net. The plot that I get is something like this:

(using the "sweep type" linear)

and this:

(using the "sweep type" logarithm, with 30 points per decade) 

I think that this has nothing to do with the open loop frequency response of the converter, because it doesn't look like the typical frequency response of the converter in open loop (it looks more like the frequency response of an OPAMP, even though the gain is not so high) - this taking into account some results that we can find through the web, like for example here: http://ecee.colorado.edu/~ecen5807/course_material/MATLAB/MATLAB_Simulink_introduction.pdf in page 18, or even though the presentation that you have posted here. I can't find that "peak" on the frequency response, but maybe it might be related to the losses in the circuit or maybe because of my operating frequency, 500MHz?

NOTES: I tried to select other nets on the schematic (just to test) but I didn't got any interesting result.

Besides that, I tried to get the frequency response selecting the other existing options, like the Voltage Gain (numerator I selected the Vout net and the denominator I selected the net where I have the VDC source connected to the VCVS), but nothing special happened.

Can you give me any clue? What I am doing wrong? I think I did as you told me (at least it was as I have interpreted):

"I suggest that you put your PAC source at a node of your circuit where you have an unmodulated signal. (I presume that is at the VDC source) This would mean that you include the circuit that converts a DC voltage to the duty cycle of the converter. (It was what I did, I used the VCVS with the VDC @ the - terminal, the duty-cycle is the output of the VCVS). Put a DC source with the correct voltage at its input and set its PAC magnitude to 1 (It was what I did, as you can see in the picture above - vdc_config). Make sure that in your netlist, the PSS analysis appears before the PAC analysis; it seems like you had an error in your simulation setup."

I am really looking forward for your reply. Thank you in advance.

Kind regards. 

I believe that your simulation setup is correct. The fact that you do not see peaking is probably due to losses in your circuit.

By the way, using a voltage-limited vcvs as the comparator was a good choice as it avoids the problem described in http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426.

Hi there Frank,

Yes, I came up with this idea after I had some problems with that "hidden state" detail. Because I don't have much experience (I would say none) with VerilogA I decided to do that with the VCVS. I was planning to construct the feedback loop main blocks through VerilogA (at least the comparator, an OPAMP, etc) but because of this issue I will try to do everything with VCVS (I will have to do some research if this is possible - Does anyone knows if it is possible?)

So all the configurations that I have done and the PAC Source positioning are correct? Is that it? (even though you have said that you believe that the setup is correct) Question: 1) Is there anyway that I could confirm this through another method? For example MATLAB and see if the results are the same? 2) Is there any problem for this purpose, use the PAC Magnitude field on the VDC SOURCE to perform the PAC Analysi? 3) In this case, the frequency response that I am seeing is the converter + pwm modulator (that 1/Vm model for the PWM). Is it?

Now, can I do the same thing, perform the PAC Analysis but now inserting "the PAC source" on the Power Supply to see the frequency response from the output to the input? I don't know if make sense to ask this plot, because, from what I have read, the transfer function that we need to design the controller is the Vout(s)/d(s).

I have done a similar experience using a LC filter and the configuration with VCVS + VDC Source + Vpulse configured to get a sawtooth based on a application note and I got similar results.

The circuit:

Frequency response:

I used the pretty same configurations.

EDIT: The red response is with the resistor modeling the inductor and capacitor internal resistance and the green one is wth the resistors equal to zero (no losses). Allow me to ask you a question regarding this: If you notice, the gain of the filter is above 0dB while, if you look here: http://www.ti.com/lit/an/slva301/slva301.pdf at page 10 & 11 you'll see the filter I am talking about. There you can see that the gain is on 0dB. What might causing this discrepancy? Maybe because I am using a Square wave at the input? If so, How can I put a sinusoidal input while preserving that VDC node (unmodulated) to perform the PAC Analysis? Or I can use directly the VSIN and perform the PSS + PAC analysis?

Another detail is that I have simulated the LC filter from the buck converter in the same fashion that I did with above mentioned one and there I got a slight "peak". In this case there are no RDS(on) from the MOSFETs.

I forgot to post here the frequency response of the converter magnitude in dB and phase:

A curious thing is that the phase plot @ the crossover frequency has a positive value. Should not be negative? I did the same with the filter I post above and I got this:

The same result in the sense that the phase has a positive value. Should not be negative too?

Kind regards and thank you so much for your availability Frank.

You can easily verify the DC gain. Increase the value of the DC source at the input by a small amount (1 mV or 10 mV, for example) and observe how much the output voltage changes due to this. Check if this ratio corresponds to the low-frequency gain that you have simulated (8 dB or so according to your plot).

In principle, you can also do this at higher frequencies: add a sine source with a small amplitude at the input and observe the amplitude (and phase) of the sine at the output. Depending on the ratio between the input frequency and the switching frequency, this might take rather long to simulate, however (and possibly cause convergence problems in pss analysis: use tran analysis in this case).

You can also test your approach with the example given at http://edn.com/design/analog/4327245/Periodic-steady-state-and-small-signal-analyses-of-switching-regulators where you can see the expected results and can also download the netlists to verify your setup.

It should be possible to build simple models for your feedback loop with controlled sources and passive components.

If you want to examine a time-continuous filter, you should put an AC source at the input (AC magnitude set to 1) and perform an AC analysis.

Why do you think that the phase at the crossover frequency of the transfer functions you plotted should be negative? You will have to design the feedback circuit in such a way that the loop gain satisfies the conditions for stability. 

Hi Frank,

Regarding the DC gain, what I did was: find the linear unities from the 7.67dB, which corresponds to 2.418.

Then I increased the value of the VDC source, from 500mV to 510mV.

The output voltage @ 500mV was varying from 1.251V to 1.2799V which corresponds to  28.9mV of riple. I found the mean value: 1.265V;

The output voltage @ 510mV was varying from 1.227V to 1.255V which corresponds to 28mV of ripple. I found the mean value: 1.241V;

If we multiply the linear unities of the gain (2.418) by the 10mV increase that gives 24.18mV.

If we subtract the obtained voltages for the 10mV increase on the VDC source, we get  24mV.

Is this what you were saying?

However, there is an issue here: If we are incresing the VDC source what we are doing is reducing the duty cycle, so of course the output voltage would be lower. In this case we can analyze the DC gain in this fashion? Regarding that if we have a DC gain we would have an increase on the signal output. I don't know if I made myself clear.

For the case at higher frequencies, I must insert a VSIN source in series with the VDC source (that is located at the "minus" signal of the VCVS)? Is that it?

Concerning the filter, I remembered that and I got the same results when simulating with a VSIN at the input of the filter. However I didn't understood well those 5kHz that in the application note from TI they refer. They say that the cut-off frequency is around 5KHz. From what I know the cut-off frequency is measured 3 dB bellow the DC gain (right?) and in my case I get 7.5KHz.

That suggestion that you gave me I will give it a try later. I will try to setup the same circuit that is presented on that article and see if I can get the same results. I'll let you know.

"Why do you think that the phase at the crossover frequency of the transfer functions you plotted should be negative? You will have to design the feedback circuit in such a way that the loop gain satisfies the conditions for stability."

Well, I said that because it was something that I found to be common in all the frequency responses I saw around the web and books. Maybe the switching frequency has here some influence, since all that converters are operating at a very low frequency compared to mine.

Thank again for your patience.

I am looking forward for your reply.

Kind regards.

I am happy to see that your results for the DC gain match the PAC results very well. Regarding your "issue": Please think about what a phase of 180 degrees at DC means.

You can either insert a VSIN source in series with the VDC source or replace the VDC source by a VSIN source and set the DC value of the VSIN source correctly (and also its PAC magnitude if you want to perform a PAC analysis).

The cutoff frequency can be defined in different ways (although 3 dB below DC gain is frequently used). They are also writing "approximately 5 kHz", so maybe they are just rounding off. 

Frank, regarding the insetion of the VSIN source in series with the VDC source (or the replacement that you talked about) I tried to simulate this using the transient analysis and at the output I got the output voltage modulated, as you can see bellow:

To be honest I don't know what this information means.

I used an amplitude of 100mV and a frequency os 100MHz (this was chosen randomly).What concerns to the amplitude, the output modulated signal has a lower value. About the phase, well, they seem to be in phase, right? What can we conclude from here?

What we are doing here remembers me the way that inverters work, to produce that 50Hz output frequency.

Nothing comes into my mind regatding that 180 degree @ DC!

Kind regards.

EDIT: Frank I tried to simulate the circuit from this website: http://edn.com/design/analog/4327245/Periodic-steady-state-and-small-signal-analyses-of-switching-regulators but without success.

First I was doing a mistake, I was using a simple PMOS and DIODE from the analogLib. After a spectre error referring to the model I discovered that the author of the article maybe had is own PMOS and DIODE model/parameters and he didn't posted that in the article. He has this:

// PMOS model

include "cmos_definition.scs" 

Even though there is nothing related to the DIODE maybe he has that diode model insed that file. He has the model name as DIODEideal. However, from what I have searched, I found that we need to put the model name in the analogLib PMOS transistor which appears within the schematic symbol, that in this case he has PMOS, but the name where he have the model is cmos_definition.scs.

Whatever. I used a PMOS from my tech lib. With the same dimension.

After replacing that PMOS I ran a simulation and an error appeared again. Now was the diode. I used a tech lib DIODE. I set the DIODE L and W to 25u than used a multiplier of 5.

The schematic that I used was the same as the author but without the error amplifier, the comparator from the PWM, and all that passive components.  Instead of those I used that setup with the VCVS. Another change that I did was the power supply voltage, I used 3.3V. The sawtooth generator I have setup exactly the same as he has in the netlist and from what we can see on the PSS analysis plot, he has the control voltage around 1V, that was what I used too in my VDC source in the VCVS.

After running a simulation PSS, PAC and TRAN I ploted the Vout (PSS) and I had an output voltage around 200mV which is very low. Tried to plot the frequency response and it was a bit different, starting from the gain value, which was very lower (-25dB), of course.

I don't know if this problem might be related to the way the signal is presented to the PMOS gate (through the VCVS). 

I am out of any ideas.

Can you give a type or so?