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Is it possible to interrupt a transient simulation on a triggering event?

Hi,

I use to use virtuoso IC 6.1.5-64b, ADE & spectre for my simulations and I wonder if it's possible to raise an interrupt on a transient simulation based on a given event. I know that we can assert some warnings using the analog device checking interface, but is it possible to extent the use of this feature or another to modulate the transient analysis duration?

I have a simulation composed of 2 phases:

- a 1st phase where a capacitance is getting slowly discharged. This may last a few hundreds of ms but this represents a very short simulation time. In corner cases, the duration may vary by a few ms, so I can't exactly predict it.

- a 2nd phase where this capacitor is recharged. This phase may last a few hundreds of us, but as it implies running an oscillator at a few MHz, this is very consuming in term of simulation time.

In order to optimize my simulation time, I would like to trigger the activation of the 2nd phase (I have a signal providing this info), simulate a few microseconds (I don't need the complete charge cycle) and then stop the simulation. Setting a fixed simulation time doesn't do the job as I can't predict the exact duration of the 1st phase, so I take the risk either of missing the 2nd phase or getting it completely, which is very long...

Any idea of a way to proceed?

Best regards,

Thibault

Frank Wiedmann over 10 years ago

I suggest that you write some VerilogA code that calls the $finish function when you want to stop the simulation (see for example http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11556554).
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Thib over 10 years ago

Thanks a lot Frank. This is exactly what I needed and that works simply and perfectly well!
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