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Drain & Source are swapped in netlist after Assura RCX!! Help me please!

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Hi,

I'm working on the phisical verification using an Assura flow, there's
two files: RSF_pre and T35FL.pre .. The first is the control file, and the other is the rules file.
When running:
>> assura RSF_pre
and checking the output netlist, I noticed that all MOSFET transistors
have thier Source and drain swapped!!! What is the possible reason
that can cause such swapping???

BTW, where can I find documents about this topic? I have Cadence and Assura installed at my company.

Could any one help me please?
Thanks in advance,
Ahmad


Originally posted in cdnusers.org by ahmad_abdulghany

Parents

  • Posted By bthayer on 9/12/2007 2:44 PM
    Did you check the pins in the layout & symbol? Is the schematic hooked up correctly (symbols are not upside down or something)?


    Thank you for replying...

    Actually, I don't have the schematic, But I compared extraction results against Calibre results, and Calibre is more convinient with the layout file i have.
    I think this is a rule file issue..
    Any other suggestion?

    Thanks again,
    Ahmad


    Originally posted in cdnusers.org by ahmad_abdulghany
Reply

  • Posted By bthayer on 9/12/2007 2:44 PM
    Did you check the pins in the layout & symbol? Is the schematic hooked up correctly (symbols are not upside down or something)?


    Thank you for replying...

    Actually, I don't have the schematic, But I compared extraction results against Calibre results, and Calibre is more convinient with the layout file i have.
    I think this is a rule file issue..
    Any other suggestion?

    Thanks again,
    Ahmad


    Originally posted in cdnusers.org by ahmad_abdulghany
Children
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