Extract netlist from layout

Hello all,

I am a digital design engineer and am trying to simulate power up/down behavior of a small system using Virtuoso.
The flow I followed: make a 32-bit adder in VHDL, synthesize the design using RTLCompiler, place&route using Encounter, extract GDSII with Encounter (including the GDSII of the standard cells used). Next I import the GDSII in Virtuso and I can see the layout.

What I would now want to do is to simulate the design using the Virtuso Analog Environment and see how much current is going into the vdd of the design when switching power. For doing this I got told that you first need a netlist of the whole design, and this is where I got stuck. I can extract the netlist of the adder from Encounter, but I don't have the schematics of my standard cells.

On www.iaik.tugraz.at/.../index.php a method is explained to extract the netlist from layout using Diva. For this a rule file is required, but when checking the foundry website the rule files for diva are only available for older technologies. Rule files for Assura available, but when I try to use the extarct.rul file in that package in Diva I get a bunch of errors on the file syntax.

Is it possible to extract the netlist using Assura?
Or do you know if it is possible to convert an Assura extract rules file to a Diva extract rules file?

Thanks,

Michael