Layout problem . yellow warning - how to remove it?

Hi guys,

Hope everything is going well.

I have posted in another forum this problem and, for conveniance I will copy to here the content. It is more easy for me, than trying to re-write in another way:

The layout that I am doing is from a 3-current mirror OTA. It is designed alone, in a separated schematic from the rest of the blocks - more, all the blocks were separated, that is, I did sub-blocks and in the end I have put them together. To do the layout I use each separated block (sub-block).

So this layout is being made apart from the rest of the other block.

I am facing a problem as you can see in the picture bellow:

[url=http://postimg.org/image/4nnq3v57t/][img]s28.postimg.org/.../url]
http://s9.postimg.org/6rjwwn97z/111111.png

I have join the drain and source of two transistor (diff. pair) in a interdigitated fashion. When I did this, cadence started to show a yellow warning.

The configuration is something like:

A BB AA BB AA BB ... BB A

The first transistor (A) has is drain in the left. Then his source is connected to the source of the second transistor (B) then his drain is connected to the third transistor (second B) drain and so on.

The pattern then becomes something like drain - source - drain - source - etc.

I am using pcells by selecting in the schematic the transistor I want and then in the layout generate from the selected (...).

For example, I started a few moments ago to design the layout of the active load of the diff. pair and only by joining the Source of transistor A with the source of transistor B (I remember that I have flipped horizontally the B transistor in order to put the S in the right position to join with the source of transistor A) that crappy warning yellow rectangle appeared!

I though that, because I am flipping horizontally the transistor B, I changed the order that cadence see the source and drain. This make sense? Don't know.

Picture 1:

[url=http://postimg.org/image/b9ka85p5n/][img]s17.postimg.org/.../url]

http://s4.postimg.org/s5qftd9a5/333333333.png

Picture 2:

[url=http://postimg.org/image/wj907xrnb/][img]s23.postimg.org/.../url]

Another thing that I though, but is awkward(!) is that, because I am joining the S of MOST A with the S of MOST B (flipped horizontally) the NWELL (white) line will be super-imposed to each other.

If you notice in Picture 1, the warning yellow box starts at one limit of the NWELL layer of transistor B and stops at the other limit of the NWELL of transistor A.

Do you understand what I mean?

Don't know if it make sense!

It is a curious thing. This because, as you can see from the picture, when I just put together each transistor by the limit NWELL layer nothing happens. However, when I join the D with D and S with S, automatically cadence yellow box warning pops up.

Regards and thanks in advance.