Identify the logic function of a layout

Hi Goncalo,

this layout represents a so-call complex, or a compound logic gate

It looks like a ORAND gate followed by an inverter. (I hope I got that right)

That is, a 2-input OR gate feeding a 2 input AND gate The output of the AND gate is inverted

These gates are used because it can save space.

If you know the cellname of this layout, the function is probably contained in it's name (eg 21OAI perhaps).

Do a search for complex logic gates using the string AOI and OAI in your search.

Hope this helps

Hello Colin and thank you very much for your help! I was wrong regarding the inputs, it will have 3 inputs.

I've searched a bit and I think this is a 3 input AOI. If it is a 3 input AOI, this one will be a 2 input AOI am I right?:

ALSO, I became a bit confused about the next layout. What would be the logic function of this layout?:

This one has two inputs (a,b) and two outputs (y1,y2).

THANK YOU VERY MUCH for your help and kindness :)

The black and white example is a simple 2-input NAND gate followed by an inverter (So, a 2 input AND gate).

The last example is not recognizable.

There is an inverter on the left and right. But the layout in the middle is incomplete.

I am guessing that the layout should represent a clock buffer with inverting and non inverting outputs.

But, the transistor in the middle has not been created correctly.

So, it's hard to say...

Colin

I was just about to reply the same as Colin - the last example appears to have an inverter on the left, but the outputs is not connected. The lower middle nmos has the source floating - and the source of the top middle pmos is connected to the a input. It's very odd and doesn't appear to be anything useful.

BTW, it should be pretty straightforward for you to draw out the schematics for these, and they are quite easy to recognize once you've done that... At the very least, you could write out a truth table (or even just simulate them) to work out the function.

Regards,

Andrew.

Hello Colin and Andrew, thank you very much for your time :)

Thanks to your help I'm starting to get it, but I have only three more examples that I'm not sure if I'm right about the implemented logic function.

With your expertise I'm sure that you can quickly identify the logic functions implemented.

The first layout has two inputs (a,b) and two outputs (y1,y2) in an N-WELL technology and I'm not sure if this is a NAND?:

It says that it has 2 outputs, so I'm not sure if it is really a NAND.

The second layout is this one and I'm not sure if it is a XOR?:

The third and final layout is this one, with two inputs (a,b) and one output (Y) in an N-WELL technology, what would be the logic function?:

THANK YOU VERY MUCH again! I'm very grateful for your help and knowing the function of these 3 layouts will help me a lot understanding it, doing some reverse engineering.

I'm a student of Introduction to Microelectronics, so I'm very sorry for my basic questions, but your answers are helping me to make a progress :)

The top one appears to have three inputs and one output (there are three unconnected gate strips, and only one metal output region). The logic seems a little odd, because if all three inputs are high, then the output will be low, and assuming the inputs are called a, b, c (left to right gates), then if a is low, or b+c are low, then the output will be high. If however a is high and either b or c is low (but not both), then the output will be floating.

The middle layout is too hard to follow in the black and white picture - it's hard to see where the inputs and outputs are or what is connected.

The bottom is a 2-input OR gate. (it's a 2 input NOR gate with an inverter on the output).

Not sure what this has to do with Cadence because from the top picture you aren't using a Cadence layout editor as far as I can see...

Maybe you should speak to your supervisor or tutor on your course?

Regards,

Andrew.