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Checking connectivity on a large array of metal structures

oldnick

I'm having trouble figuring out how to verify a design of a CCD array we have. The array consists of many rows/columns of pixels which, but there is no schematic for the pixel as the layout is 4 metal rectangle which stretch across the width of the cell with vias to the substrate (the substrate has several customer specific layers which allow a CCD to be fabricated on CMOS technology - we have no access to what these layers are). These 4 metal lines are the CCD clocks, p1, p2, p3, p4. It is at the left side of the array every all clock phases are connected together (al p1's connected together, all p2's connected together) and then out to the 4 pads.

one missing via etc. will render the array useless so a robust verification strategy is required, but I'm having trouble figuring out how to do this as there is no circuit to be used for comparison. Ideally we'd want a continuity check from say, each of the clock lines in every pixel to the pad. The best I can see so far is highlight nets, then zoom in and check every thing by eye. But in a mega pixel camera this isn't feasible or robust.

I've tried making a schematic with just 4 pins and comparing that against a pixel, this lvs's with a single pixel, but as soon as you combine 2 or more it falls over.

There must be a way of doing this. Is there some connectivity check between 2 points I could write a script to repeat for a whole array counting the errors or something? 

Any help would be greatly appreciated.

  • IYou could  trace the nets using dbGetTrueOverlaps. Find all the vias then using the same command, find the overlapping connected metal. Lots of hierarchy you will have to work with and it would take some time to get the coding right, let alone run the check.

    The simplest alternative in my mind is to create a schematic and run LVS. Create symbols representing each type of pixel and create the array and add the connectivity in a schematic based on the parameters used to create the layout. Then run LVS. This moves the net tracing to a better suited tool. I've done this before with complex memory generators so a CCD should be pretty straight forward.

    Ted

  • Hi Ted,

    The 2nd option you mention sounds most like the one I've been trying to figure out how to do for a few weeks with no success. There are no structures in the pixel that cadence 'knows about', just 4 strips of metal1 and a contact to the substrate on each strip. There are a couple of layers, active, poly, NSD and a customer specific layer (we don't know what they are as it's a 3rd party custom process), but no device to speak off. 

    I can create a schematic with only 4 pins (an empty schematic in effect), and LVS that against a single pixel and that passes. However, the LVS is looking at the layout and seeing no circuits, then looking at an empty layout and thus giving a match (0 = 0). If I tie 2 pixels together, there are now nets connecting the pins in the schematic so LVS now accepts they exist in the schematic, but  still 'sees nothing' in the layout so gives a mismatch as the nets in the schematic aren't there.

    I was wondering if there was a way to do an RC extraction (or just extract R), so that I can create a schematic with 4 resistors, the resistances of the metal tracks. But I don't know how I would get LVS to accept this, as there are no actual instances of resistors in the layout, just the metal tracks.

    There must be a  way of doing this surely.

  • You may have to write a little LVS deck which determines how to create a model of the device from the shapes. The model is created by looking at shape interaction, you may put a recognition layer on the lower level cell used to create the array. The model recognition is defined in the LVS deck and the is dependent on the LVS tool. => Layer A and Layer B and recognitionLayer = aPixel

    Ted

  • Cheers Ted,

    That's a lot of help. That's not something I knew about until you mentioned it. I've had a quick read of the LVS user guide and I think I understand what has to be done and it sounds like it'll work. I just need to figure out how to do it now...I think the CTM layer that is peculiar to the pixels will make this a bit easier.

    Cheers.

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