• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. LVS out of swap memory

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 124
  • Views 13485
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

LVS out of swap memory

archive
archive over 17 years ago

I am running LVS on a large pixel array (16-mega pixel) which contains nothing but repeating the unit pixel. The pixel array is organized in a hierarchal systems consisting of cells that group increasing number of pixels (ie 1-pixel cell, 10-pixel cell made of 10 of 1-pixel cells, 100-pixel cell made of 10 of 10-pixel cells, 1000-pixel cell made of 10 of 100-pixel cells, and so on). Both the schematic and the layout have the same structure and pins. My problem now is that when I run LVS it eats up all the memory available on the system (4 GB, the maximum memory a 32-bit system can have) and LVS stops. I thought by structuring my design in a hierarchal way the runtime and memory requirements would be minimized. Am I doing something wrong so LVS would need > 4 GB of memory? Or this is the case for everyone who need to check large array designs (such as cameral pixel arrays or memory arrays)?


Originally posted in cdnusers.org by wochiang
  • Cancel
  • archive
    archive over 17 years ago

    It might help if you said which LVS tool you're using... since Cadence have four, it's a little hard to tell what you're doing.

    Andrew.


    Originally posted in cdnusers.org by adbeckett
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • archive
    archive over 17 years ago

    It's Assura LVS.


    Originally posted in cdnusers.org by wochiang
    • Cancel
    • Vote Up 0 Vote Down
    • Cancel

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information