How to use constraints to create a symmetric layout (with abutted MOS) using schematicXL and Layout XL (No modgens)

Hello,

I am trying to layout a simple diff-pair and cascode cell (no tail and load devices, that is separate) using Virtuoso schematicXL and layoutXL.

I am trying to use constraints. I do not have license for LayoutGXL (so I cannot do Modgens). This is a 16nm process

Let the 2 cascode devices be A and B, and let the dummies be D.

I need something like this in the layout :  ( DDDDAAAAAAAADDDDDDDDBBBBBBBBDDDD)

How do I go about doing this without using modgens?

I have tried defining constraints (symmetry in placement and routing, and matched instance color), but I am unable to abut devices if I do that.

Another issue is: All the bold and underlined Ds above share the source with A or B, but have gates same as other Ds.

Hence, they need to be defined as separate devices in the schematic and appear as a separate single device when you generate layout from source. This means more maneuvering to place each of these single devices.

I am not getting any benefit so far from the many options in Layout XL. Are there any settings/controls that I can tweak to make better use of the tool?

Any help much appreciated. Regards,