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Problem with MOS Bulk Routing Parasitic Resistance Extraction

Stepan

Hi,

During the Spectre netlist generation process, I have found out that the Assura QRC extractor includes the parasitic resistances of the MOS transistor bulk routing in the extraction view:

rg58 (vdda \5\:vdda) resistor r=24.5376 c=0

But, it skips connecting this parasitic resistor to the bulk of the transistor:

M10 (\3\:vout \5\:nclk \2\:vin vdda) p_lv_18_mm w=1.92e-06 l=2.4e-07 ad=2.224e-13 as=2.224e-13 pd=2.0u ps=2.0u m=(1)*(1)

From the line above, you can see that it circumvents the parasitic resistor and connects the bulk directly to the polarization net vdda (NOT \5\:vdda)

As a result, the simulation netlist generated from this extracted view is also incorrect.

 

I have tried two different technologies with two different design kits and both have the same issue. Two kits are:

1. Virtuoso Design Environment version IC6.1.3.500.13 with Cadence Extraction QRC - Parasitic Extractor - Version 8.1.4-p002.

2. Virtuoso Design Environment version IC6.1.5-64b.500.132 with Cadence Extraction QRC - Parasitic Extractor - Version 11.1.2-p106.


Is there any way to fix this problem? Can it be done by modifying the configuration script or updating the kit?

Thanks,

Stepan.

Parents

  • Hi Stepan

    The difficulty is, the bulk is under the transistor - and how do you know which substrate tap is the one that is connecting to it? One approach might be to write rules in the LVS to create pseudo islands or wells under the transistors - these don't exist in reality, but you could effectively try to treat each of these regions as unconnected from each other, and only connected via the substrate taps. Of course, you'd need to ensure that these substrate regions are big enough to include a substrate tap near the transistor.

    Then the behaviour would be similar to your n-wells (if a p-substate process) or vice-versa.

    All this would involve changing the LVS extraction rule deck. 

    There's not (as far as I know) any magic switch to do this isolation of the bulks automatically (at least not making sure they are connected up to a suitable tap).

    Regards,

    Andrew.

Reply

  • Hi Stepan

    The difficulty is, the bulk is under the transistor - and how do you know which substrate tap is the one that is connecting to it? One approach might be to write rules in the LVS to create pseudo islands or wells under the transistors - these don't exist in reality, but you could effectively try to treat each of these regions as unconnected from each other, and only connected via the substrate taps. Of course, you'd need to ensure that these substrate regions are big enough to include a substrate tap near the transistor.

    Then the behaviour would be similar to your n-wells (if a p-substate process) or vice-versa.

    All this would involve changing the LVS extraction rule deck. 

    There's not (as far as I know) any magic switch to do this isolation of the bulks automatically (at least not making sure they are connected up to a suitable tap).

    Regards,

    Andrew.

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