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Problem with MOS Bulk Routing Parasitic Resistance Extraction

Stepan

Hi,

During the Spectre netlist generation process, I have found out that the Assura QRC extractor includes the parasitic resistances of the MOS transistor bulk routing in the extraction view:

rg58 (vdda \5\:vdda) resistor r=24.5376 c=0

But, it skips connecting this parasitic resistor to the bulk of the transistor:

M10 (\3\:vout \5\:nclk \2\:vin vdda) p_lv_18_mm w=1.92e-06 l=2.4e-07 ad=2.224e-13 as=2.224e-13 pd=2.0u ps=2.0u m=(1)*(1)

From the line above, you can see that it circumvents the parasitic resistor and connects the bulk directly to the polarization net vdda (NOT \5\:vdda)

As a result, the simulation netlist generated from this extracted view is also incorrect.

 

I have tried two different technologies with two different design kits and both have the same issue. Two kits are:

1. Virtuoso Design Environment version IC6.1.3.500.13 with Cadence Extraction QRC - Parasitic Extractor - Version 8.1.4-p002.

2. Virtuoso Design Environment version IC6.1.5-64b.500.132 with Cadence Extraction QRC - Parasitic Extractor - Version 11.1.2-p106.


Is there any way to fix this problem? Can it be done by modifying the configuration script or updating the kit?

Thanks,

Stepan.

Parents

  • Thanks Andrew,


    Following your opinion, I delved into LVS extraction rule scripts.

    The PMOS transistor is extracted such:

    extractMOS( "P_18_MM" pgate_mm ply("G") psd("S" "D") wel("B") flagMalformed )


    where wel is previously declared as:

    wel= geomAndNot( nwell welres )

    being nwell:

    nwell = geomAndNot( NWEL TWEL )

    and NWEL:

    NWEL = layer( "NWEL" type("drawing") )

    A part, the connectivity section mandates:

    geomStamp( wel ntap )

    geomConnect(
    .....
                via( nsdcon   M1  nsd ntap )

    .....)


    According to these lines, it seems there is a clear connection definition reduced to few connection layers. I tried the following experiment:

    Two separated NWELLs connected by a resistive path of M1. Each of two NWELLs contains one PMOS transistor with all terminals shortcircuited to the well polarization bias. And I would expect to obtain two separated nodes between two different NWELLS connected through this resistive M1 path. However, after extraction, the bulk terminal of this transistors is shortcircuited. Curiously, it does not happen with the sources of the same transistors which are connected through the parasitic resistance of M1 path.

    Is there anything to see with the ivpcell of the transistor? Can I act on it to solve the problem?

    Thank you,

    Stepan.

Reply

  • Thanks Andrew,


    Following your opinion, I delved into LVS extraction rule scripts.

    The PMOS transistor is extracted such:

    extractMOS( "P_18_MM" pgate_mm ply("G") psd("S" "D") wel("B") flagMalformed )


    where wel is previously declared as:

    wel= geomAndNot( nwell welres )

    being nwell:

    nwell = geomAndNot( NWEL TWEL )

    and NWEL:

    NWEL = layer( "NWEL" type("drawing") )

    A part, the connectivity section mandates:

    geomStamp( wel ntap )

    geomConnect(
    .....
                via( nsdcon   M1  nsd ntap )

    .....)


    According to these lines, it seems there is a clear connection definition reduced to few connection layers. I tried the following experiment:

    Two separated NWELLs connected by a resistive path of M1. Each of two NWELLs contains one PMOS transistor with all terminals shortcircuited to the well polarization bias. And I would expect to obtain two separated nodes between two different NWELLS connected through this resistive M1 path. However, after extraction, the bulk terminal of this transistors is shortcircuited. Curiously, it does not happen with the sources of the same transistors which are connected through the parasitic resistance of M1 path.

    Is there anything to see with the ivpcell of the transistor? Can I act on it to solve the problem?

    Thank you,

    Stepan.

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