PLL spectre simulator settings

I'm encountering a weird problem in my 2nd order filter integerN PLL. 
Situation: The PLL i'm designing (transistor level) is composed of a PFD, (with buffers) charge pump with opamp as bootstrap, RC C filter and LC tank VCO. A x64 is performed. (Fvco = 2.4GHz)

Depending on the settings of the transient simulation, the PLL shows a limit cycle beahvior that is similar to deadzone. As shown in the figure, the control voltage (AND phase!!!) shows jumps (both Vc and phase jumps as the phase should be the integrated one of Vc).

Setting 1: traponly, 5ps maxstep, conservative  -> limit cycle
Setting 2: traponly, 0.5ps maxstrep , conservative -> no limit cycle.

Transient noise on with fmax=30GHz

I use traponly since it gives faster startup times.

When I remove the VCO and place a linear VCO model in the circuit, the cycle is gone with setting 1. An ideal charge pump does not solve the issue. I checked all PFD signals but they are wide enough.

I checked my PFD + charge pump in open loop simulations but no deadzone is present (sweeping time difference between reference clock and fb clock and measuring the average output current.)

The PLL system is stable, checked in many calculations, model simulations...

Sadly 0.5ps timesteps take a long time to simulate several useconds.

Anyone knows what the origin of this problem is? 
numerical issues or circuit issue? 

Could the simulation settings cause deadzone somewhere. Since the problem is resolved by removing the VCO, have you ever seen deadzone occuring in a vco?

The image shows the control voltage of the VCO and the phase (time difference from VCOout to and ideal 2.4GHz clock)

Thanks in advance